SDI II Intel® FPGA IP User Guide

ID 683133
Date 10/21/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.1.3. Handling Transceiver in Intel® Agilex™ F-tile Devices

F-tile PMA/FEC Direct PHY Intel FPGA IP supports two clocking modes: the System PLL Clocking Mode and the Traditional PMA Clocking Mode.

Note: If you need to dynamically reconfigure the PHY, only System PLL clocking mode is supported.