1.1. Altera IP Catalog and Parameter Editor
1.2. Installing and Licensing Altera* IP Cores
1.3. Best Practices for Altera* IP
1.4. IP General Settings
1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
1.6. Generating IP Cores ( Quartus® Prime Standard Edition)
1.7. Generating Example Designs for Altera* IP
1.8. Modifying an IP Variation
1.9. Upgrading IP Cores
1.10. Simulating Altera* IP Cores
1.11. Synthesizing IP Cores in Other EDA Tools
1.12. Support for the IEEE 1735 Encryption Standard
1.13. Introduction to Altera* IP Cores Revision History
1.14. Introduction to Altera* IP Cores Archives
1.10.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
1.10.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts
1.10.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts
1.10.4.1.4. Sourcing QuestaSim* Simulator Setup Scripts
1.10.4.1.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts
1.10.4.1.6. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts
1.12.2.2. Using Supported Simulator Mode for IEEE1735 Encryption
The IEEE1735 Standalone Encryptor can also encrypt a file to be read into simulators that the Quartus® Prime supports.
Refer to Supported Simulators for the current supported list.
In Supported Simulator Mode takes the Encryptor takes in one source file, and then generates one encrypted file. The --simulation option encrypts the files for all four supported simulators simultaneously. To encrypt for only one or more specific simulators, specify the simulator by specifying a value for the --simulation option. The valid options are aldec, cadence, mentor, synopsys.
- Use one of the following commands to use Supported Simulator Mode for encryption. Use a comma delimiter to specify multiple simulators. Do not enter spaces between the options. For example, --simulation=aldec,cadence.
- Verilog HDL:
encrypt_1735 --simulation --language=verilog <file_name>.v
- VHDL:
encrypt_1735 --simulation --language=vhdl <file_name>.vhd
The Encryptor creates an encrypted file with the same file name, but with a new extension, such as some_file.vp and some_file.vhdp.
- Verilog HDL:
- To optionally change the name of the output file name, specify the -o option. For example:
- Verilog:
encrypt_1735 --simulation --language=verilog -o=<new_file_name>.v \ <file_name>.v
- VHDL:
encrypt_1735 --simulation --language=vhdl -o=<new_file_name>.vhd \ <file_name>.vhd
Note: If you are encrypting files that are called by name in other parts of the source code, such as Verilog `include files, you must use the correct encrypted filename when you reference the files. Use the -o option to create the encrypted file with the original filename, so that the name does not include the default “p” in the extension (for example, <included_file_name>.v instead of <included_file_name>.vp). - Verilog: