1.1. Altera IP Catalog and Parameter Editor
1.2. Installing and Licensing Altera* IP Cores
1.3. Best Practices for Altera* IP
1.4. IP General Settings
1.5. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
1.6. Generating IP Cores ( Quartus® Prime Standard Edition)
1.7. Generating Example Designs for Altera* IP
1.8. Modifying an IP Variation
1.9. Upgrading IP Cores
1.10. Simulating Altera* IP Cores
1.11. Synthesizing IP Cores in Other EDA Tools
1.12. Support for the IEEE 1735 Encryption Standard
1.13. Introduction to Altera* IP Cores Revision History
1.14. Introduction to Altera* IP Cores Archives
1.10.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
1.10.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts
1.10.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts
1.10.4.1.4. Sourcing QuestaSim* Simulator Setup Scripts
1.10.4.1.5. Sourcing Synopsys VCS* (2-Step) Simulator Setup Scripts
1.10.4.1.6. Sourcing Synopsys VCS* (3-Step) Simulator Setup Scripts
1.12.1. Introduction to the IEEE 1735 Standalone Encryptor
The IEEE P1735-2014 standard addresses issues of encryption, rights management, and licensing to enable interoperability of protected Electronic Design Intellectual Property (EDIP or IP) across various tools and vendors.
The IEEE 1735 Standalone Encryptor adheres to the IEEE P1735-2014 Version 1 standard, and generates a digital envelope containing encrypted IP that you can safely distribute among partners. The standalone encryptor provides an efficient method to encrypt intellectual property in Verilog or VHDL source format for the Quartus® Prime software and supported simulators.
The IEEE 1735 Standalone Encryptor ships with the Quartus® Prime software beginning with version 17.0. You can use the IEEE 1735 Standalone Encryptor from the command-line, similar to other Quartus® Prime executables.