F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 4/01/2024
Document Table of Contents

4.4.2. RX Reset and Initialization Sequence

The RX reset sequence for F-Tile Serial Lite IV Intel® FPGA IP is as follows:
  1. Assert rx_pcs_fec_phy_reset_n, rx_core_rst_n, reconfig_reset, and reconfig_sl_reset simultaneously to reset the F-Tile hard IP, MAC, and reconfiguration blocks. Release rx_pcs_fec_phy_reset_n and reconfiguration reset after waiting for rx_reset_ack to ensure the blocks are properly reset.
  2. The IP then asserts the phy_rx_pcs_ready signal after the custom PCS reset is released, to indicate RX PHY is ready for transmission.
  3. Release the rx_core_rst_n signal after phy_rx_pcs_ready signal goes high.
  4. The IP starts the lane alignment process after the RX MAC reset is released and upon receiving ALIGN paired with START/END or END/START CW.
  5. The RX deskew block asserts the rx_link_up signal once alignment for all lanes has complete.
  6. The IP then asserts the rx_link_up signal to the user logic to indicate that the RX link is ready to start data reception.
Figure 25. RX Reset and Initialization Timing Diagram