F-Tile Serial Lite IV Intel® FPGA IP User Guide

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ID 683074
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Control and Status Registers 8. Designing with F-Tile Serial Lite IV Intel® FPGA IP 9. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation 4.6. 32-bit Soft CWBIN Counters 4.7. i_stats_snapshot Port 4.8. Deterministic Latency
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Control and Status Registers x
7.1. F-Tile Serial Lite IV Intel® FPGA IP Soft CSR
8. Designing with F-Tile Serial Lite IV Intel® FPGA IP x
8.1. Reset Guidelines 8.2. Error Handling Guidelines 8.3. Analog Parameter Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals
7. Control and Status Registers
8. Designing with F-Tile Serial Lite IV Intel® FPGA IP
9. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide

2.5. Resource Utilization and Latency

The resources and latency for the F-Tile Serial Lite IV Intel® FPGA IP were obtained from the Quartus® Prime Pro Edition software version 22.3.

Table 5.   Intel® Agilex™ 7 F-Tile Serial Lite IV Intel® FPGA IP Resource UtilizationThe latency measurement is based on the round trip latency from the TX core input to the RX core output.
Transceiver Type Variant Number of Data Lanes Mode RS-FEC ALM Dedicated Logic Registers ALUTs Memory 20K Latency (TX core clock cycle)
FGT 32 Gbps NRZ 16 Basic Disabled 8349 26960 5407 0 77
16 Full Disabled 8993 26480 5562 0 77
16 Basic Enabled 8504 26648 5543 0 203
16 Full Enabled 9076 27277 5677 0 203
58 Gbps PAM4 12 Basic Enabled 14465 44407 8590 0 162
12 Full Enabled 15271 44354 8777 0 162
FHT 29 Gbps NRZ 4 Basic Disabled 2265 6766 1538 0 80
4 Full Disabled 2387 7003 1605 0 80
4 Basic Enabled 2320 6894 1597 0 203
4 Full Enabled 2429 7101 1666 0 203
58 Gbps NRZ 4 Basic Enabled 4957 14481 3118 0 154
4 Full Enabled 5245 15015 3196 0 154
58 Gbps PAM4 4 Basic Enabled 4971 14500 3115 0 163
4 Full Enabled 5244 14983 3193 0 163
116 Gbps PAM4 4 Basic Enabled 9462 27647 5347 0 134
4 Full Enabled 9764 28559 5485 0 134
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