1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
|Intel® Quartus® Prime Design Suite 23.1|
|IP Version 8.1.0|
This document describes IP features, architecture description, steps to generate, and guidelines to design the F-Tile Serial Lite IV Intel® FPGA IP using the F-tile transceivers in Intel® Agilex™ 7 devices.
- Design architects to make IP selection during the system-level design planning phase
- Hardware designers when integrating the IP into their system-level design
- Validation engineers during the system-level simulation and hardware validation phases
For other documents related to the F-Tile Serial Lite IV Intel® FPGA IP, refer to the related information.
Acronyms and Glossary
|RS-FEC||Reed-Solomon Forward Error Correction|
|PMA||Physical Medium Attachment|
|PAM4||Pulse-Amplitude Modulation 4-Level|
|PCS||Physical Coding Sublayer|
|MII||Media Independent Interface|
|XGMII||10 Gigabit Media Independent Interface|
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