F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 4/11/2023

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1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 23.1
IP Version 8.1.0

This document describes IP features, architecture description, steps to generate, and guidelines to design the F-Tile Serial Lite IV Intel® FPGA IP using the F-tile transceivers in Intel® Agilex™ 7 devices.

Intended Audience

This document is intended for the following users:
  • Design architects to make IP selection during the system-level design planning phase
  • Hardware designers when integrating the IP into their system-level design
  • Validation engineers during the system-level simulation and hardware validation phases

Related Documents

For other documents related to the F-Tile Serial Lite IV Intel® FPGA IP, refer to the related information.

Acronyms and Glossary

Table 1.  Acronym List
Acronym Expansion
CW Control Word
RS-FEC Reed-Solomon Forward Error Correction
PMA Physical Medium Attachment
TX Transmitter
RX Receiver
PAM4 Pulse-Amplitude Modulation 4-Level
NRZ Non-return-to-zero
PCS Physical Coding Sublayer
MII Media Independent Interface
XGMII 10 Gigabit Media Independent Interface