F-Tile Serial Lite IV Intel® FPGA IP User Guide

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ID 683074
Date 4/11/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Control and Status Registers 8. Designing with F-Tile Serial Lite IV Intel® FPGA IP 9. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation 4.6. 32-bit Soft CWBIN Counters 4.7. i_stats_snapshot Port
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Control and Status Registers x
7.1. F-Tile Serial Lite IV Intel® FPGA IP Soft CSR
8. Designing with F-Tile Serial Lite IV Intel® FPGA IP x
8.1. Reset Guidelines 8.2. Error Handling Guidelines
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals
7. Control and Status Registers
8. Designing with F-Tile Serial Lite IV Intel® FPGA IP
9. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide

6.5. PMA Signals

Table 28.  PMA SignalsIn this table, N represents the number of lanes set in the IP parameter editor.
Name Width Direction Clock Domain Description

phy_tx_lanes_stable

  • N (1 Gb to <29 Gb)
  • N*2 (29 Gb to <58 Gb)
  • N*4 (≥58 Gb)
Output Asynchronous When asserted, indicates TX datapath is ready to send data.

tx_pll_locked

  • N (1 Gb to <29 Gb)
  • N*2 (29 Gb to <58 Gb)
  • N*4 (≥58 Gb)
Output Asynchronous When asserted, indicates the TX PLL has achieved lock status.

phy_ehip_ready

  • N (1 Gb to <29 Gb)
  • N*2 (29 Gb to <58 Gb)
  • N*4 (≥58 Gb)
Output Asynchronous When asserted, indicates that the custom PCS has completed internal initialization and ready for transmission.

This signal asserts after tx_pcs_fec_phy_reset_n and tx_pcs_fec_phy_reset_nare deasserted.

tx_serial_data

N

Output TX serial clock TX serial pins.

rx_serial_data

N

Input RX serial clock RX serial pins.
phy_rx_block_lock
  • N (1 Gb to <29 Gb)
  • N*2 (29 Gb to <58 Gb)
  • N*4 (≥58 Gb)
Output Asynchronous When asserted, indicates that the 66b block alignment has completed for the lanes.
rx_cdr_lock
  • N (1 Gb to <29 Gb)
  • N*2 (29 Gb to <58 Gb)
  • N*4 (≥58 Gb)
Output Asynchronous When asserted, indicates that the recovered clocks are locked to data.
phy_rx_pcs_ready
  • N (1 Gb to <29 Gb)
  • N*2 (29 Gb to <58 Gb)
  • N*4 (≥58 Gb)
Output Asynchronous When asserted, indicates that the RX lanes of the corresponding Ethernet channel are fully aligned and ready to receive data.
phy_rx_hi_ber
  • N (1 Gb to <29 Gb)
  • N*2 (29 Gb to <58 Gb)
  • N*4 (≥58 Gb)
Output Asynchronous When asserted, indicates that the RX PCS of the corresponding Ethernet channel is in a HI BER state.
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