F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 4/28/2022
Public

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4.1.4. TX MII Encoder

The TX MII encoder handles the packet transmission from the MAC to the TX PCS.
The following figure shows the data pattern on the 8-bit MII bus in PAM4 modulation mode. The START and END CW appear once in every two MII lanes.
Figure 17. PAM4 Modulation Mode MII Data Pattern
The following figure shows the data pattern on the 8-bit MII bus in NRZ modulation mode. The START and END CW appear in every MII lanes.
Figure 18. NRZ Modulation Mode MII Data Pattern