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1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with F-Tile Serial Lite IV Intel® FPGA IP 8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
4.2.5. RX CW Removal
This block decodes the CWs and sends data to the user logic using the Avalon® streaming interface after the removal of the CWs.
When there is no valid data available, the RX CW removal block deasserts the rx_avs_valid signal.
In FULL mode, if the user bit is set, this block asserts the rx_is_usr_cmd signal and the data in the first clock cycle is used as user-defined information or command.
When rx_avs_ready deasserts and rx_avs_valid asserts, the RX CW removal block generates an error condition to the user logic.
The Avalon® streaming signals related to this block are as follow:
- rx_is_usr_cmd (only available in Full mode)
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