F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 4/28/2022

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Document Table of Contents

4.2.5. RX CW Removal

This block decodes the CWs and sends data to the user logic using the Avalon® streaming interface after the removal of the CWs.

When there is no valid data available, the RX CW removal block deasserts the rx_avs_valid signal.

In FULL mode, if the user bit is set, this block asserts the rx_is_usr_cmd signal and the data in the first clock cycle is used as user-defined information or command.

When rx_avs_ready deasserts and rx_avs_valid asserts, the RX CW removal block generates an error condition to the user logic.

The Avalon® streaming signals related to this block are as follow:
  • rx_avs_startofpacket
  • rx_avs_endofpacket
  • rx_avs_channel
  • rx_avs_empty
  • rx_avs_data
  • rx_avs_valid
  • rx_num_valid_bytes_eob
  • rx_is_usr_cmd (only available in Full mode)