F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 4/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2. Supported Features

The following table lists the features available in F-Tile Serial Lite IV Intel® FPGA IP:
Table 4.   F-Tile Serial Lite IV Intel® FPGA IP Features
Feature Description
Data Transfer
  • For PAM4 mode:
    • FHT supports only 56.1, 58, and 116 Gbps per lane with a maximum of 4 lanes.
    • FGT supports up to 58 Gbps per lane with a maximum of 12 lanes.
    Refer to Table 1 for more details on the supported transceiver data rates for PAM4 mode.
  • For NRZ mode:
    • FHT supports only 28.05 and 58 Gbps per lane with a maximum of 4 lanes.
    • FGT is supporting up to 28.05 Gbps per lane with a maximum of 16 lanes.
    Refer to Table 1 for more details on the supported transceiver data rates for NRZ mode.
  • Supports continuous streaming (Basic) or packet (Full) modes.
  • Supports low overhead frame packets.
  • Supports byte granularity transfer for every burst size.
  • Supports user-initiated or automatic lane alignment.
  • Supports programmable alignment period.
PCS
  • Uses hard IP logic that interfaces with Intel® Agilex™ F-tile transceivers for soft logic resource reduction.
  • Supports PAM4 modulation mode for 100GBASE-KP4 specification. RS-FEC is always enabled in this modulation mode.
  • Supports NRZ with optional RS-FEC modulation mode.
  • Supports 64b/66b encoding decoding.
Error Detection and Handling
  • Supports CRC error checking on TX and RX data paths.
  • Supports RX link error checking.
  • Supports RX PCS error detection.
Interfaces
  • Supports only full duplex packet transfer with independent links.
  • Uses point-to-point interconnect to multiple FPGA devices with low transfer latency.
  • Supports user-defined commands.