F-Tile Serial Lite IV Intel® FPGA IP User Guide

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ID 683074
Date 4/28/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with F-Tile Serial Lite IV Intel® FPGA IP 8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Designing with F-Tile Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with F-Tile Serial Lite IV Intel® FPGA IP
8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives
9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide

5. Parameters

Table 18.   F-Tile Serial Lite IV Intel® FPGA IP Parameter Description
Parameter Value Default Description
General Design Options
PMA modulation type
  • PAM4
  • NRZ
PAM4 Select the PCS modulation mode.
PMA Type
  • FHT
  • FGT
FGT Selects the transceiver type.
PMA data rate
  • For PAM4 mode:
    • FGT transceiver type: 20 Gbps – 58 Gbps
    • FHT transceiver type: 56.1 Gbps, 58 Gbps, 116 Gbps
  • For NRZ mode:
    • FGT transceiver type: 10 Gbps – 28.05 Gbps
    • FHT transceiver type: 28.05 Gbps, 58 Gbps

56.1 (FGT/FHT PAM4)

28.05 Gbps (FGT/FHT NRZ)

 Specifies the effective data rate at the output of the transceiver incorporating transmission and other overheads. The value is calculated by the IP by rounding up to 1 decimal place in Gbps unit.
PMA mode
  • Duplex
  • Tx
  • Rx
Duplex For FHT transceiver type, the supported direction is duplex only. For FGT transceiver type, the supported direction is Duplex, Tx, and Rx.
Number of PMA lanes
  • For PAM4 mode:
    • 1 to 12
  • For NRZ mode:
    • 1 to 16
2 Select the number of lanes. For simplex design, the supported number of lanes is 1.
PLL reference clock frequency
  • For FHT transceiver type: 156.25 MHz
  • For FGT transceiver type: 27.5 MHz – 379.84375 MHz, depending on the selected transceiver data rate.
  • For FHT transceiver type: 156.25 MHz
  • For FGT transceiver type: 165 MHz
 Specifies the reference clock frequency of the transceiver.
System PLL reference clock frequency — 170 MHz Only available for FHT transceiver type. Specifies the System PLL reference clock and will be used as input of F-Tile Reference and System PLL Clocks Intel FPGA IP to generate the System PLL clock.
System PLL frequency — 876.5625 MHz Specifies the System PLL clock frequency.
Alignment Period 128 – 65536 128 Specifies the alignment marker period.

The value must be x2.

Enable RS-FEC

Enable

Disable

 Enable Turn on to enable the RS-FEC feature.

For PAM4 PCS modulation mode, RS-FEC is always enabled.
User Interface
Streaming mode
  • FULL
  • BASIC
Full Select the data streaming for the IP.

Full: This mode sends a start-of-packet and end-of-packet cycle within a frame.

Basic: This is a pure streaming mode where data is sent without a start-of-packet, empty, and end-of-packet to increase bandwidth.
Enable CRC

Enable

Disable

 Disable Turn on to enable CRC error detection and correction.
Enable auto alignment

Enable

Disable

 Disable Turn on to enable automatic lane alignment feature.
Enable debug endpoint

Enable

Disable

 Disable When ON, the F-Tile Serial Lite IV Intel® FPGA IP includes an embedded Debug Endpoint that internally connects to the Avalon® memory-mapped interface. The IP can perform certain tests and debug functions through JTAG using the System Console. Default value is Off.
Simplex Merging (This parameter setting is only available when you select FGT dual simplex design.)
RSFEC enabled on the other Serial Lite IV Simplex IP placed at the same FGT channel(s)

Enable

Disable

 Disable

Turn on this option if you require a mixture of configuration with RS-FEC enabled and disabled for the F-Tile Serial Lite IV Intel FPGA IP in a dual simplex design for NRZ transceiver mode, where both TX and RX are placed on the same FGT channel(s).

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