Visible to Intel only — GUID: kws1617333197031
Ixiasoft
Visible to Intel only — GUID: kws1617333197031
Ixiasoft
6.5. PMA Signals
Name | Width | Direction | Clock Domain | Description |
---|---|---|---|---|
phy_tx_lanes_stable |
N*2 (PAM4 mode) N (NRZ mode) |
Output | Asynchronous | When asserted, indicates TX datapath is ready to send data. |
tx_pll_locked |
N*2 (PAM4 mode) N (NRZ mode) |
Output | Asynchronous | When asserted, indicates the TX PLL has achieved lock status. |
phy_ehip_ready |
N*2 (PAM4 mode) N (NRZ mode) |
Output | Asynchronous | When asserted, indicates that the custom PCS has completed internal initialization and ready for transmission. This signal asserts after tx_pcs_fec_phy_reset_n and tx_pcs_fec_phy_reset_nare deasserted. |
tx_serial_data |
N |
Output | TX serial clock | TX serial pins. |
rx_serial_data |
N |
Input | RX serial clock | RX serial pins. |
phy_rx_block_lock | N*2 (PAM4 mode) N (NRZ mode) |
Output | Asynchronous | When asserted, indicates that the 66b block alignment has completed for the lanes. |
rx_cdr_lock | N*2 (PAM4 mode) N (NRZ mode) |
Output | Asynchronous | When asserted, indicates that the recovered clocks are locked to data. |
phy_rx_pcs_ready | N*2 (PAM4 mode) N (NRZ mode) |
Output | Asynchronous | When asserted, indicates that the RX lanes of the corresponding Ethernet channel are fully aligned and ready to receive data. |
phy_rx_hi_ber | N*2 (PAM4 mode) N (NRZ mode) |
Output | Asynchronous | When asserted, indicates that the RX PCS of the corresponding Ethernet channel is in a HI BER state. |
Did you find the information on this page useful?
Feedback Message
Characters remaining: