4.4.4. RX Flow Control Interface
The RX flow control interface provides information on the application's available RX buffer space to the PCIe Hard IP in a time-division multiplexing (TDM) manner. It reports the space available in number of TLPs.
The RX flow control interface is optional and disabled by default in the IP GUI. If disabled, it indicates that there is no limit in the application RX buffer space.
- Posted (P) transactions: TLPs that do not require a response.
- Non-posted (NP) transactions: TLPs that require a completion.
- Completions (CPL): TLPs that respond to non-posted transactions.
|Memory Read Lock|
|Completion with Data|
|Completion Lock with Data|
|Fetch and Add AtomicOp||Non-posted|
|RX Buffer Segment||core_x16 (Port 0)||core_x8 (Port 1)||core_x4 (Ports 2/3)|
|Scaled Flow Control Disabled (Credit)||Scaled Flow Control Enabled (Scale Factor, Credit)||Scaled Flow Control Disabled (Credit)||Scaled Flow Control Enabled (Scale Factor, Credit)||Scaled Flow Control Disabled (Credit)||Scaled Flow Control Enabled (Scale Factor, Credit)|
|Posted Headers||127||3, 49||127||2. 98||127||2, 56|
|Posted Data||1456||1, 1456||760||1, 760||396||1, 396|
|Non-posted Headers||127||3, 49||127||2, 98||127||2, 56|
|Non-posted Data||392||1, 392||196||1, 196||112||1, 112|
|Signal Name||Direction||Description||Clock Domain||EP/RP/BP|
When the RX Flow Control Interface is enabled, the application can use these signals for TLP flow control. These signals indicate the application RX buffer space made available since reset/initialization.
Initially, the signals are set according to the buffer size (in terms of the number of TLPs the RX buffer can take). The value of these signals always increments and rolls over. For example, if the initial value is 0xfff, the rx_buffer_limit_i[11:0] value increments by 1 and rolls over to 0x000 when one received TLP exits the application RX buffer.
If a TLP type is blocked due to a lack of the corresponding RX buffer space in the application layer, other TLP types may bypass it per the PCIe transaction ordering rules.
Note that the initial value of rx_buffer_limit_i[11:0] cannot be larger than 2048 TLPs.
|rx_buffer_limit_tdm_idx_i[1:0]||I||These signals indicate the type of buffer for the corresponding rx_buffer_limit_i[11:0] signals. The Application Layer should provide the buffer limit information for all the enabled ports in a TDM manner. The following encodings are defined:
For more details on the usage of the scale factors, refer to Section 3.4.2 of the PCI Express Base Specification, Rev. 4.0 Version 1.0.
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