G.3.1. Debug Toolkit (DTK) Testing Process
In the case of 5x5 (Intel's recommendation), you have to test five different boards with five power cycled runs on each part or board. It means that you have to power on the board with the link under test at the L0 LTSSM state and at the desired PCIe Speed with no recoveries on the PCIe link. Then, you must load DTK, run the Eye View tool to get margins in all PCIe lanes and manually store the data samples. After, apply a power cycle to the board and repeat the process five times once that PCIe link under test is properly trained. The complete sequence must be repeated per test board (in this case five different boards or parts). Finally, you must get an average of the collected Left, Right, Up and Down margin values to compare with Margin Mask values provided in Margin Mask Values for the P-Tile Avalon Streaming Intel FPGA IP for PCI Express.
Contact Intel if there are questions or concerns with the process or the results.
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