P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683059
Date 2/01/2023

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4.13. PHY Reconfiguration Interface

The PHY reconfiguration interface is an optional Avalon® -MM slave interface with a 26‑bit address and an 8‑bit data bus. Use this bus to read the value of PHY registers.

These signals are present when you turn on Enable PHY reconfiguration on the Top-Level Settings tab using the parameter editor.

Please note that the PHY reconfiguration interface is shared among all the PMA quads.

Table 82.  PHY Reconfiguration Interface
Signal Name Direction Description Clock Domain EP/RP/BP
xcvr_reconfig_clk I

Reconfiguration clock

50 MHz - 125 MHz (Range)

100 MHz (Recommended)

xcvr_reconfig_readdata[7:0] O Avalon® -MM read data outputs xcvr_reconfig_clk EP/RP/BP
xcvr_reconfig_readdatavalid O Avalon® -MM read data valid. When asserted, the data on xcvr_reconfig_readdata[7:0] is valid. xcvr_reconfig_clk EP/RP/BP
xcvr_reconfig_write I Avalon® -MM write enable xcvr_reconfig_clk EP/RP/BP
xcvr_reconfig_read I Avalon® -MM read enable. This interface is not pipelined. You must wait for the return of the xcvr_reconfig_readdata[7:0] from the current read before starting another read operation. xcvr_reconfig_clk EP/RP/BP
xcvr_reconfig_address[25:0] I

Avalon® -MM address

[25:21] are used to indicate the Quad.

5'b00001 : Quad 0

5'b00010 : Quad 1

5'b00100 : Quad 2

5'b01000 : Quad 3

[20:0] are used to indicate the offset address.

xcvr_reconfig_clk EP/RP/BP
xcvr_reconfig_writedata[7:0] I Avalon® -MM write data inputs xcvr_reconfig_clk EP/RP/BP
xcvr_reconfig_waitrequest O When asserted, this signal indicates that the PHY is not ready to respond to a request. xcvr_reconfig_clk EP/RP/BP

Reading from the PHY Reconfiguration Interface

Reading from the PHY reconfiguration interface of the P-Tile Avalon® -ST IP for PCI Express retrieves the current value at a specific address.

Figure 48. Timing Diagram to Perform Read Operations Using the PHY Reconfiguration Interface