Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683055
Date 11/01/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.1.7. Nios II Processor Code

The Nios II processor controls the options exercised in the design example. The code also enables CRAM bits for CRC-32 error injection support. The error injection support in 10G PCS is based on groups of three channels or triplets. Setting the corresponding bit for a given channel in the triplet enables CRC error injection for all of the lanes that use any channel in the given triplet.

The design example sets the bit for channel 0 that connects to lane 0 in the design example. Therefore, CRC error injection is exercisable for lane 0 only. Refer to the Nios II processor source code (demo_control.c) for information on setting bits for other channels.