Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683055
Date 11/01/2021
Public
Document Table of Contents

3.4.1. Testbench

If your design targets Intel® Arria® 10 devices, the generated example testbench is dynamic and has the same configuration as the IP.

Note: The Intel® Arria® 10 example testbench includes the external transceiver PLL; the IP core does not include the transceiver PLL for these devices.
Figure 23. Serial Lite III Streaming Example Testbench (Duplex) for Intel® Arria® 10 Devices
Figure 24. Serial Lite III Streaming Example Testbench (Simplex) for Intel® Arria® 10 Devices