Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683055
Date 11/01/2021
Document Table of Contents

3.3. Functional Description

The design examples consist of various components. The following block diagrams show the design components and the top-level connections of the design examples.

Figure 16. Design Example for Simplex Core in Advanced Clocking Mode
Figure 17. Design Example for Duplex Core in Advanced Clocking Mode

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