Serial Lite III Streaming Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683055
Date 11/01/2021
Document Table of Contents Demo Control3.3.1.6. Demo Control

The demo control module is a Nios® II processor system, generated in Platform Designer (Standard), to control the demo hardware.

Demo control module also consists of a timer to track interrupt occurrence, Avalon® memory-mapped interface to access demo management and the Serial Lite III Streaming Intel® FPGA IP PHY interface, a reset controller, a UART interface, and an Avalon® streaming interface.

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