Intel® Quartus® Prime Pro Edition User Guide: Programmer

ID 683039
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2.2.3. Debugging the Configuration (Convert Programming Files)

Click the Advanced option in the Convert Programming Files dialog box to debug the file conversion configuration. Only choose advanced settings that apply to the design's target Intel FPGA device.

Changes in the Advanced Options dialog box affect .pof, .jic, .rpd, and .rbf file generation.

The following table describes the Advanced Options settings:

Table 6.  Advanced Options Settings
Option Setting Description Values
Disable EPCS/EPCQ ID check

Directs the FPGA to skips the EPCS/EPCQ silicon ID verification.

Applies to single and multi device AS configuration modes on all devices.

Default setting is ON (EPCS/EPCQ ID check is enabled).
Disable AS mode CONF_DONE error check

Directs the FPGA to skip the CONF_DONE error check.

Applies to single- and multi-device (AS) configuration modes on all devices.

Default setting is OFF (AS mode CONF_DONE error check is enabled).

Program Length Count adjustment

Specifies the offset you can apply to the computed PLC of the entire bitstream.

Applies to single- and multi-device (AS) configuration modes on all FPGA devices.

Integer (Default = 0)
Post-chain bitstream pad bytes Specifies the number of pad bytes appended to the end of an entire bitstream.

If the bitstream of the last device is uncompressed, default value is 0.

Otherwise, default is 2

Post-device bitstream pad bytes

Specifies the number of pad bytes appended to the end of the bitstream of a device.

Applies to all single-device configuration modes on all FPGA devices.

Zero or positive integer.

Default is 0

Bitslice Padding Value

Specifies the padding value used to prepare bitslice configuration bitstreams, such that all bitslice configuration chains simultaneously receive their final configuration data bit.

Use only in 2, 4, and 8-bit PS configuration mode, when you use an EPC device with the decompression feature enabled.

Applies to all FPGA devices that support enhanced configuration devices.

0 or 1

Default value is 1

The following table lists possible symptoms of a failing configuration, and describes the advanced options necessary for configuration debugging.

Failure Symptoms Disable EPCS/EPCQ ID Check Disable AS Mode CONF_DONE Error Check PLC Settings Post-Chain Bitstream Pad Bytes Post-Device Bitstream Pad Bytes Bitslice Padding Value
Configuration failure occurs after a configuration cycle. Yes Yes Yes 1 Yes 2
Decompression feature is enabled. Yes Yes Yes 1 Yes 2
Encryption feature is enabled. Yes Yes Yes 1 Yes 2
CONF_DONE stays low after a configuration cycle. Yes Yes 3 Yes 1 Yes 2
CONF_DONE goes high momentarily after a configuration cycle. Yes Yes 4
FPGA does not enter user mode even though CONF_DONE goes high. Yes 1 Yes 2
Configuration failure occurs at the beginning of a configuration cycle. Yes
EPCS128 Yes
Failure in .pof generation for EPC device using Intel® Quartus® Prime Convert Programming File Utility when the decompression feature is enabled. Yes
1 Use only for multi-device chain
2 Use only for single-device chain
3 Start with positive offset to the PLC settings
4 Start with negative offset to the PLC settings