Intel® Quartus® Prime Pro Edition User Guide: Programmer

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ID 683039
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel® Quartus® Prime Programmer User Guide 3. Using the Intel® Quartus® Prime Programmer 4. Using the HPS Flash Programmer A. Intel® Quartus® Prime Pro Edition User Guide: Programmer Document Archive B. Intel® Quartus® Prime Pro Edition User Guides
2. Intel® Quartus® Prime Programmer User Guide x
2.1. Generating Primary Device Programming Files 2.2. Generating Secondary Programming Files 2.3. Enabling Bitstream Security for Intel® Stratix® 10 and Intel® Agilex™ 7 Devices 2.4. Enabling Bitstream Encryption or Compression for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 2.5. Generating Programming Files for Partial Reconfiguration 2.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems 2.7. Scripting Support 2.8. Generating Programming Files Revision History
2.2. Generating Secondary Programming Files x
2.2.1. Generating Secondary Programming Files (Programming File Generator) 2.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) 2.2.3. Generating Secondary Programming Files (Settings: Programming Files Dialog Box)
2.2.1. Generating Secondary Programming Files (Programming File Generator) x
2.2.1.1. Configuration Modes (Programming File Generator) 2.2.1.2. Secondary Programming Files (Programming File Generator)
2.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) x
2.2.2.1. Secondary Programming Files (Convert Programming Files) 2.2.2.2. Configuration Modes (Convert Programming Files) 2.2.2.3. Debugging the Configuration (Convert Programming Files)
2.3. Enabling Bitstream Security for Intel® Stratix® 10 and Intel® Agilex™ 7 Devices x
2.3.1. Enabling Bitstream Authentication (Programming File Generator) 2.3.2. Specifying Additional Physical Security Settings (Programming File Generator) 2.3.3. Enabling Bitstream Encryption (Programming File Generator)
2.5. Generating Programming Files for Partial Reconfiguration x
2.5.1. Generating PR Bitstream Files 2.5.2. Partial Reconfiguration Bitstream Compatibility Checking 2.5.3. Raw Binary Programming File Byte Sequence Transmission Examples 2.5.4. Generating a Merged .pmsf File from Multiple .pmsf Files ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)
2.6. Generating Programming Files for Intel® FPGA Devices with Hard Processor Systems x
2.6.1. Generating Programming Files for HPS Boot First Boot Flows 2.6.2. Generating Programming Files for FPGA Configuration First Boot Flows
2.7. Scripting Support x
2.7.1. quartus_pfg Command Line Tool 2.7.2. quartus_cpf Command Line Tool
2.7.2. quartus_cpf Command Line Tool x
2.7.2.1. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File
3. Using the Intel® Quartus® Prime Programmer x
3.1. Intel® Quartus® Prime Programmer 3.2. Programming and Configuration Modes 3.3. Basic Device Configuration Steps 3.4. Specifying the Programming Hardware Setup 3.5. Programming with Flash Loaders 3.6. Verifying the Programming File Source with Project Hash 3.7. Using PR Bitstream Security Verification ( Intel® Stratix® 10 Designs) 3.8. Stand-Alone Programmer 3.9. Programmer Settings Reference 3.10. Scripting Support 3.11. Using the Intel® Quartus® Prime Programmer Revision History
3.4. Specifying the Programming Hardware Setup x
3.4.1. JTAG Chain Debugger Tool 3.4.2. Editing the Details of an Unknown Device 3.4.3. Running JTAG Daemon with Linux
3.4.1. JTAG Chain Debugger Tool x
3.4.1.1. JTAG Chain Integrity Tab 3.4.1.2. JTAG Chain Debugging Tab
3.5. Programming with Flash Loaders x
3.5.1. Specifying Flash Partitions 3.5.2. Full Erase of Flash Memory Sectors
3.6. Verifying the Programming File Source with Project Hash x
3.6.1. Obtaining Project Hash for Intel® Arria® 10 Devices
3.8. Stand-Alone Programmer x
3.8.1. Stand-Alone Programmer Memory Consumption
3.9. Programmer Settings Reference x
3.9.1. Device & Pin Options Dialog Box 3.9.2. More Security Options Dialog Box 3.9.3. Output Files Tab Settings (Programming File Generator) 3.9.4. Input Files Tab Settings (Programming File Generator) 3.9.5. Bitstream Co-Signing Security Settings (Programming File Generator) 3.9.6. Configuration Device Tab Settings 3.9.7. Add Partition Dialog Box (Programming File Generator) 3.9.8. Add Filesystem Dialog Box (Programming File Generator) 3.9.9. Convert Programming File Dialog Box 3.9.10. Compression and Encryption Settings (Convert Programming File) 3.9.11. SOF Data Properties Dialog Box (Convert Programming File) 3.9.12. Select Devices (Flash Loader) Dialog Box
3.10. Scripting Support x
3.10.1. The jtagconfig Debugging Tool
4. Using the HPS Flash Programmer x
4.1. HPS Flash Programmer Command-Line Utility 4.2. How the HPS Flash Programmer Works 4.3. Using the Flash Programmer from the Command Line 4.4. Supported Memory Devices 4.5. HPS Flash Programmer User Guide Revision History
4.3. Using the Flash Programmer from the Command Line x
4.3.1. HPS Flash Programmer 4.3.2. HPS Flash Programmer Command Line Examples
1. Answers to Top FAQs
2. Intel® Quartus® Prime Programmer User Guide
3. Using the Intel® Quartus® Prime Programmer
4. Using the HPS Flash Programmer
A. Intel® Quartus® Prime Pro Edition User Guide: Programmer Document Archive
B. Intel® Quartus® Prime Pro Edition User Guides

3.9.1. Device & Pin Options Dialog Box

The following tables describe Device & Pin Option settings that impact generation of primary and secondary programming files. To access these settings, click Assignments > Device > Device & Pin Options.
Table 16.  General Device OptionsAllow you to specify basic device configuration options that are independent of a specific configuration scheme. To access these settings, click Assignments > Device > Device and Pin Options > General.
Option Description
Options
Note: Not supported for Intel® Agilex™ 7 or Intel® Stratix® 10 devices.
  • Auto-restart configuration after error—restarts the configuration process automatically if a data error is encountered. If this option is turned off, you must externally direct the device to restart the configuration process if an error occurs. This option is available for passive serial and active serial configuration schemes.
  • Release clears before tri-states—releases the clear signal on registered logic cells and I/O cells before releasing the output enable override on tri-state buffers. If this option is turned off, the output enable signals are released before the clear overrides are released.
  • Enable user-supplied start-up clock (CLKUSR)—uses a user-supplied clock on the CLKUSR pin for initialization. When turned off, external circuitry is required to provide the initialization clock on the DCLK pin in the Passive Serial and Passive Parallel Synchronous configuration schemes; in the Passive Parallel Asynchronous configuration scheme, the device uses an internal initialization clock.
  • Enable device-wide reset (DEV_CLRn)—enables the DEV_CLRn pin, which allows all registers of the device to be reset by an external source. If this option is turned off, the DEV_CLRn pin is disabled when the device operates in user mode and is available as a user I/O pin.
  • Enable device-wide output enable (DEV_OE)—enables the DEV_OE pin when the device is in user mode. If this option is turned on, all outputs on the chip operate normally. When the pin is disabled, all outputs are tri-stated. If this option is turned off, the DEV_OE pin is disabled when the device operates in user mode and is available as a user I/O pin.
  • Enable INIT_DONE output—enables the INIT_DONE pin, which allows you to externally monitor when initialization is complete and the device is in user mode. If this option is turned off, the INIT_DONE pin is disabled when the device operates in user mode and is available as a user I/O pin.
  • Enable JTAG Pin Sharing—enables the JTAG pin sharing feature. The JTAGEN pin is enables and becomes a dedicated input pin in user mode. JTAG pins (TDO, TCK, TDI, and TMS pins) are available as test pins when the JTAGEN pin is pull low. JTAG pins are dedicated when the JTAGEN pin is high. If this option is turned off, the JTAGEN pin is disabled when the device operates in user mode and is available as a user I/O pin. JTAG pins are retained as dedicated JTAG pins.
  • Enable nCONFIG, nStatus, and CONF_DONE pins—enables the major configuration pins, nCONFIG, nSTATUS, and CONF_DONE pin in user mode. If this option is turned off, the nCONFIG, nSTATUS, and CONF_DONE pins are disabled when the device operates in user mode and are available as user I/O pins.
  • Enable OCT_DONE —enables the OCT_DONE pin, which controls whether the INIT_DONE pin is gated by OCT_DONE pin. If this option is turned off, the INIT_DONE pin is not gated by the OCT_DONE pin.
  • Enable security bit support—enables the security bit support, which prevents data in a device from being obtained and used to program another device. This option is available for supported device ( MAX® II, and MAX® V) families.
  • Set unused TDS pins to GND—sets the unused temperature sensing diode TSD pins, TEMPDIODEp and TEMPDIODEn to GND in the pin. By default, TSD pins are available for connection to an external temperature sensing device; however, you must manually connect the pins to GND if they are not connected. When turned on, this option updates the information in the .pin file and does not affect FPGA behavior.
  • Enable CONFIG_SEL pin—enables the BOOT_SEL pin in user mode. If this option is turned off, the BOOT_SEL pin is disabled when the device operates in user mode and is available as a user I/O pin.
  • Enable nCEO pin—enables the nCEO pin. This pin should be connected to the nCE of the succeeding device when multiple devices are being programmed. If this option is turned off, the nCEO pin is disabled when the device operates in user mode and is available as a user I/O pin.
  • Enable autonomous PCIe HIP mode—releases the PCIe HIP after periphery configuration, before device core configuration completes. This option only takes effect if CvP mode is disabled.
  • Enable the HPS early release of HPS IO—releases the HPS shared I/O bank after the IOCSR programming.
Auto usercode Sets the JTAG user code to match the checksum value of the device programming file. The programming file is a .pof for non-volatile devices, or an .sof for SRAM-based devices. If you turn on this option, the JTAG user code option is not available.
JTAG user code Specifies a hexadecimal number for the device selected for the current Compiler settings. The JTAG user code is an extension of the option register. This data can be read with the JTAG USERCODE instruction. If you turn on Auto usercode, this option is not available.
In-system programming clamp state Allows you to specify the state that the pins take during in-system programming for used pins that do not have an in-system programming clamp state assignment. Unused pins and dedicated inputs must always be tri-stated for in-system programming. Used pins are tri-stated by default during in-system programming, which electrically isolates the device from other devices on the board. At times, however, in order to prevent system damage you may want to specify the logic level for used pins during in-system programming. The following settings are available:
  • Tri-state—the pins are tri-stated.
  • High—the pins drive VCCIO.
  • Low—the pins drive GND.
  • Sample and Sustain—the pins drive the level captured during the SAMPLE/PRELOAD JTAG instruction.
Configuration clock source Specifies the clock source for device initialization (the duration between CONF_DONE signal went high and before INIT_DONE signal goes high).

For AS x1 or AS x4 configuration mode, you can select either Internal Oscillator or CLKUSR pin only. The DCLK pin is an illegal option for AS mode. In 14 nm device families, only Internal Oscillator or OSC_CLK_1 pins are available.

Device initialization clock source Specifies the clock source for device initialization (the duration between CONF_DONE signal went high and before INIT_DONE signal goes high).

For AS x1 or AS x4 configuration mode, you can select either Internal Oscillator or CLKUSR pin only. The DCLK pin is an illegal option for AS mode. In 14 nm device families, only Internal Oscillator or OSC_CLK_1 pins are available.

Table 17.  Configuration OptionsAllow you to specify the configuration scheme, configuration device and pin options, serial clock source, and other options for subsequent device configuration with your programming bitstream. To access these settings, click Assignments > Device > Device and Pin Options > Configuration. Disabled options are unavailable for the current device or configuration mode.
Option Description
Configuration scheme Specifies the scheme of configuration for generation of appropriate primary and secondary programming files, such as Active Serial x4. Only options appropriate for the current Configuration Scheme are available.
Configuration Device Allows you to specify options for an external configuration device that stores and loads configuration data.
  • Configuration device I/O voltage—specifies the VCCIO voltage of the configuration pins for the current configuration scheme of the target device. This option is available for supported device families.
  • Force VCCIO voltage to be compatible with configuration I/O voltage—forces the VCCIO voltage of the configuration pins to be the same as the configuration device I/O voltage. If you turn off this option, the VCCIO voltage of the configuration pins may vary depending on the I/O standards used in the I/O banks containing the configuration pins. This option is available for supported device families.
Configuration Pin Options Enables or disables operation of specific device configuration pins for status monitoring, SEU error detection, CvP, and other configuration pin options.
Generate compressed bitstreams Generates compressed bitstreams and enables bitstream decompression in the target device.
Active serial clock source Specifies the configuration clock source for Active Serial programming. Options range from 12.5 MHz to 100 MHz.
VID Operation Mode Enables Voltage Identification logic in the target device with selected operation mode. The available options are PMBus Master or PMBus Slave.
HPS/FPGA configuration order For hard processor system (HPS) configuration, specifies the order of configuration between the HPS and FPGA. The options are HPS First, After INIT_DONE, and When requested by FPGA.
HPS debug access port
  • Disabled—the HPS JTAG is not enabled.
  • HPS Pins—the HPS JTAG is routed to the HPS dedicated I/O.
  • SDM Pins—the HPS JTAG is chained to the FPGA JTAG.
Disable Register Power-Up Initialization Specifies whether the Assembler generates a bit stream with register power-up initialization.
Table 18.  Unused Pin OptionsAllow you specify the reserve state of all the unused pins on the device. To access, click Assignments > Device > Device and Pin Options > Unused Pins. Disabled options are unavailable for the current device or configuration mode.
Option Description
Reserve all unused pins
  • As input tri-stated—the pins reserve as tri-state input pins.
  • As output driving ground—the pins reserve as output pins and drive the ground signal.
  • As output driving an unspecified signal—the pins reserve as output pins and drive any signal.
  • As input tri-stated with bus-hold circuitry—the pins reserve as tri-state input pins with bus-hold circuitry.
  • As input tri-stated with weak pull-up—the pins reserve as tri-state input pins with weak pull-up resistors.
Table 19.  Dual-Purpose Pin OptionsAllow you to specify whether the associated dual-purpose pin is reserved, and the reservation purpose. To access, click Assignments > Device > Device and Pin Options > Dual-Purpose Pins. Disabled options are unavailable for the current device or configuration mode.
Option Description
Dual-purpose pins
  • Use as regular I/O—the dual-purpose pin is not reserved. Rather the I/O pin is in in user mode.
  • Use as programming pin—the nCEO pin is reserved as a dedicated programming pin.
  • As input tri-stated—the dual-purpose pin is reserved as an input pin.
  • As output driving ground—the dual-purpose pin is reserved as an output pin and drives the ground signal.
  • As output driving an unspecified signal—the dual-purpose pin is reserved as an output pin and drives any signal.
  • Compiler configured—the Compiler automatically selects the best reserve setting for the dual-purpose pin, considering the current configuration scheme, and whether the pins are only used for configuration. If your design uses the Active Parallel configuration scheme and the Programmer does not communicate directly with the parallel flash device in user mode, you should reserve all dual-purpose pins connected to the parallel flash device as Compiler configured.
Table 20.  Board Trace Model OptionsFor Intel® Cyclone® 10 GX designs only, allows you to specify the board trace, termination, and capacitive load parameters for each I/O standard. The board trace model parameters then apply to all output or bidirectional pins that you assign with the specified I/O standard. Board trace model parameters do not apply if you assign them to anything other than an output or bidirectional pin. You can create board trace model assignments for individual output or bidirectional pins in the Pin Planner. To access, click Assignments > Device > Device and Pin Options > Board Trace Model. Disabled options are unavailable for the current device or configuration mode.
Option Description
I/O standard Specifies the supported I/O standard, such as Differential 1.8-V SSTL Class II.
Board trace model Lists the board trace model parameters, with units, and values for the specified I/O standard. You can change the value of each parameter. The board trace model assignments apply to all output and bidirectional pins with the specified I/O standard assigned to them.
Table 21.  I/O Timing OptionsAllow you to specify the node at which output I/O timing terminates. To access, click Assignments > Device > Device and Pin Options > I/O Timing. Disabled options are unavailable for the current device or configuration mode.
Option Description
Default timing I/O endpoint Specify Near end or Far end.
Table 22.  Voltage OptionsAllow you to specify the default I/O bank voltage for pins on the target device. Also displays the core voltage of the device or other internal voltage information. To access, click Assignments > Device > Device and Pin Options > Voltage. Disabled options are unavailable for the current device or configuration mode.
Option Description
Default I/O standard Specify 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 LVTTL, or 3.0 LVCMOS.
Table 23.  Error Detection CRC OptionsAllow you to specify whether to use error detection cyclic redundancy check (CRC) and the value by which you want to divide the error check frequency for the currently selected device. To access, click Assignments > Device > Device and Pin Options > Error Detection CRC. Disabled options are unavailable for the current device or configuration mode.
Option Description
Enable Error Detection CRC_ERROR pin Enables error detection CRC and CRC_ERROR pin usage for the targeted device. This check determines the validity of the programming data in the device. Any changes in the data while the device is in operation generates an error.
Note: Not available for Intel® Agilex™ 7 or Intel® Stratix® 10 devices.
Enable Open Drain on CRC Error pin

Sets the CRC ERROR pin as an open-drain pin. This action decouples the voltage level of the CRC ERROR pin from VCCIO voltage. When you turn on this option, you must connect a pull-up resistor to the CRC ERROR pin.

Note: Not available for Intel® Agilex™ 7 or Intel® Stratix® 10 devices.
Enable error detection check Enables error detection CRC checking to verify the validity of programming data in the device, and reports any changes in the data while the device is in operation.
Minimum SEU interval Specifies the minimum time interval between two checks of the same bit. Setting to 0 means check as frequently as possible. Setting to a large value saves power. The unit of interval is millisecond. The maximum allowed number of intervals is 10000.
Enable internal scrubbing Specifies use of internal scrubbing to correct any detected single error or double adjacent error within the core configuration memory while the device is still running.
Generate SEU sensitivity map file Generates a Single Event Upset Sensitivity Map file. This file allows you to enable the Advanced SEU detection feature.
Allow SEU fault injection Allows the injection of fault patterns to test for SEU.
Table 24.  CvP SettingsSpecifies the configuration mode for Configuration via Protocol (CvP). To access, click Assignments > Device > Device and Pin Options > CvP Settings. Disabled options are unavailable for the current device or configuration mode.
Option Description
Configuration via protocol In Initialization and update mode, the periphery image stores in an external configuration device and loads the image into the FPGA through a conventional configuration scheme. The core image stores in a host memory and loads into the FPGA through the PCIe link. In Core initialization mode, the periphery image stores in an external configuration device and loads into the FPGA through the conventional configuration scheme. The core image is stores in a host memory and is loads into the FPGA through the PCIe link. In Core update mode, the FPGA device is initialized after initial system power up by loading the full configuration image from the external local configuration device to the FPGA. You can use the PCIe link to perform one or more FPGA core image update through this mode. In the Off mode, CvP is turned off.
Enable CvP_CONFDONE pin Indicates that the device finished core programming in Configuration via Protocol mode. If this option is turned off, the CvP_CONFDONE pin is disabled when the device operates in user mode and is available as a user I/O pin.
Note: Not available for Intel® Agilex™ 7 or Intel® Stratix® 10 devices.
Enable open drain on CvP_CONFDONE pin Enables the open drain on the CvP_CONFDONE pin.
Note: Not available for Intel® Agilex™ 7 or Intel® Stratix® 10 devices.
Table 25.  Partial Reconfiguration OptionsSpecifies generation of secondary programming files that partial reconfiguration requires. To access, click Assignments > Device > Device and Pin Options > Partial Reconfiguration. Disabled options are unavailable for the current device or configuration mode.
Option Description
Enable partial reconfiguration pins Allows you to enable the PR_REQUEST, PR_READY, PR_ERROR, PR_DONE, DCLK, and DATA[31..0] pins. These pins are needed to support partial reconfiguration (PR) with an external host. An external host uses the PR_REQUEST pin to request partial reconfiguration, the PR_READY pin to determine if the device is ready to receive programming data, the PR_ERROR pin to externally monitor programming errors, and the PR_DONE pin to indicate the device finished programming. If this option is turned off, these pins are not available as PR pins when the device operates in user mode and the dual-purpose programming pins are available as user I/O pins.
Note: Not available for Intel® Agilex™ 7 or Intel® Stratix® 10 devices.
Enable open drain on partial reconfiguration pins Allows you to specify an open drain on the PR_READY, PR_ERROR, PR_DONE Partial Reconfiguration pins.
Note: Not available for Intel® Agilex™ 7 or Intel® Stratix® 10 devices.
Generate Partial-Masked SOF files Generates a Partial-Masked SRAM Object file (.pmsf) containing both configuration data and region definitions that can be used to re-configure a device region. If this option is turned on, the .pmsf generates instead of a Mask Settings file (.msf).
Generate Partial Reconfiguration RBF Generates a Partial Reconfiguration Raw Binary File (.rbf) containing configuration data that an intelligent external controller can use to reconfigure the portion of target device.
Table 26.  Power Management & VID OptionsFor Intel® Stratix® 10 and Intel® Agilex™ 7 devices only, specifies options for managing power, such as the bus speed mode and the address of the voltage regulator when in PMBus Master mode. To access, click Assignments > Device > Device and Pin Options > Power Management & VID Options. Disabled options are unavailable for the current device or configuration mode.
Option Description
Bus speed mode Specifies the bus speed mode (for example, 100 KHz or 400 KHz) in PMBus Master mode.
Slave device type Specifies the slave device type when the target FPGA device is in PMBus master mode. Available options are ED8401, EM21XX, EM22XX, ISL82XX, LTM4677, and Other.
Device address in PMBus Slave mode Specifies the starting 00 device address when in PMBus Slave mode.
PMBus device 0 slave address through PMBus device 7 slave address Specifies 7-bit hexadecimal value (without leading prefix 0x). For example, 7F for the slave address of a voltage regulator when in PMBus Master mode. You must specify a non-zero address.
Voltage output format Specifies the Auto discovery, Direct format, or Linear format output voltage format when in PMBus Master mode
Direct format coefficient (m,b,R) Specifies direct format coefficient m, b, or R when in PMBus Master mode. Signed integer between -32768 and 32767. Coefficient m is the slope coefficient. Coefficient b is the offset. Coefficient R is the exponent. Refer to the PMBus device manufacturer product documentation for these values. You must set this parameter when output voltage format of PMBus device is Direct format or Auto discovery format. You must specify a non-zero address when the output voltage format of PMBus device is in Direct format.
Linear format N Specifies linear format N when in PMBus Master mode. Signed integer between -16 and 15. This is the exponent for the mantissa for the output voltage related command when VOUT format is set to Linear format. Refer to the PMBus device manufacturer product documentation for these values. You must specify a non-zero value for Linear format.
Translated voltage value unit Specifies the Volts or Millivolts output voltage format when in PMBus Master mode.
Enable PAGE command The FPGA PMBus master uses PAGE command to set all output channels on registered regulator modules to respond to VOUT_COMMAND.
Table 27.  Assembler Security SettingsFor Intel® Stratix® 10 devices, specifies settings for programming bitstream authentication, encryption, scrambling, and other eFuse enabled security options. To access these settings, click Assignments > Device > Device and Pin Options > Security. Disabled options are unavailable for the current device or configuration mode.
Option Description
Quartus Key File Specifies the first level signature chain file (.qky) that you generate. This chain includes the root key (.pem) and one or more design signing keys (.pem) required to sign the bitstream and allow access to the FPGA when using authentication or encryption.
Encryption key storage select Specifies the location that stores the .qek key file. You can select either Battery Backup RAM or eFuses for storage.
Encryption update ratio Specifies the ratio of configuration bits compared to the number of key updates required for bitstream decryption. You can select either 31:1 (the key must change 1 time every 31 bits) or Disabled (no update required). Encryption supports up to 20 intermediate keys.
Enable scrambling Scrambles the configuration bitstream.
More Options Opens the More Security Options dialog box for specifying additional physical security options.
Table 28.  Configuration PIN Dialog BoxFor Intel® Stratix® 10 devices, allows you to enable or disable specific configuration pins. For example, you can enable the CvP_CONFDONE pin, which indicates that the device finished core programming in Configuration via Protocol mode. To access these settings, click Assignments > Device > Device and Pin Options > Configuration Pin Options. Disabled options are unavailable for the current device or configuration mode.
Option Values Description
USE PWRMGT_SCL output SDM_1O0| SDM_IO14

This is a required PMBus interface for the power management when the VID operation mode is the PMBus Master or PMBus Slave mode.

Disable this pin for a non-SmartVID device.

Intel® recommends using the SDM_IO14 pin for this function.

Use PWRMGT_SDA output SDM_1O11| SDM_1O12|SDM_1O16

This is a required PMBus interface for the power management when the VID operation mode is the PMBus Master or PMBus Slave mode.

Disable this pin for a non-SmartVID device.

Intel® recommends using the SDM_IO11 pin for this function.

Use PWRMGT_ALERT output SDM_1O0|SDM_1O12

This is a required PMBus interface for the power management that is used only in the PMBus Slave mode.

Disable this pin for a non-SmartVID device.

Intel® recommends using the SDM_IO12 pin for this function.

USE CONF_DONE output SDM_100, SDM_1010 - SDM_1016 Implement CONF_DONE using appropriate configuration pin resource.
USE INIT_DONE output SDM_100, SDM_1010 - SDM_1016 Enables the INIT_DONE pin, which allows you to externally monitor when initialization is completed and the device is in user mode. If this option is turned off, the INIT_DONE pin is disabled when the device operates in user mode and is available as a user I/O pin.
USE CVPCONF_DONE output SDM_100, SDM_1010 - SDM_1016 Enables the CVP_CONFDONE pin, which indicates that the device finished core programming in Configuration via Protocol mode. If this option is turned off, the CVP_CONFDONE pin is disabled when the device operates in user mode and is available as a user I/O pin.
USE SEU_ERROR output SDM_100, SDM_1010 - SDM_1016 Enables the SEU_ERROR pin for use in single event upset error detection.
USE UIB CATTRIP output SDM_100, SDM_1010 - SDM_1016 Enables UIB_CATTRIP output to indicate an extreme over-temperature conditioning resulted from UIB usage.
USE HPS cold nreset SDM_100, SDM_1010 - SDM_1016 An optional reset input that cold resets only the HPS and is configured for bidirectional operation.
Direct to factory image SDM_100, SDM_1010 - SDM_1016 If this pin asserted then device loads the factory image as the first image after boot without attempting to load any application image.
USE DATA LOCK output SDM_100, SDM_1010 - SDM_1016 Output to indicate DIBs on both die in the same package is ready for data transfer.
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