Intel® Quartus® Prime Pro Edition User Guide: Programmer

ID 683039
Date 4/03/2023

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2.6.2. Generating Programming Files for FPGA Configuration First Boot Flows

In FPGA Configuration First boot flows, the FPGA core and periphery are configured first. After that, the HPS can optionally be booted.

To generate programming files for FPGA Configuration First boot flows

  1. Generate the primary programming files for your design, as Generating Primary Device Programming Files describes.
  2. Click File > Programming File Generator.
  3. For Device family, select your target device. The options available in the Programming File Generator change dynamically, according to your device and configuration mode selection.
  4. For Configuration mode, select an Active Serial mode that your device supports. Configuration Modes (Programming File Generator) describes all modes.
  5. On the Output Files tab, select JTAG Indirect Configuration File (.jic), then select the following files:
    • Raw Binary File of Programming Helper Image (.rbf)

    • Raw Programming Data File (.rpd)

    Secondary Programming Files (Programming File Generator) describes all output files.

  6. On the Output Files tab, select Raw Programming Data File (.rpd) and click Edit.
  7. Optional: Optional: In the RPD Properties dialog box, set Bit swap to On.
    Important: This step may or may not be required, depending on the external programmer that you use.
  8. Specify the Output directory and Name for the file you generate. Output Files Tab Settings (Programming File Generator) describes all options.
  9. On the Input Files tab, click Add Bitstream to add your .sof file and then edit its properties:
    1. Select the .sof file and click Properties.
    2. In the Bootloader field of Input File Properties dialog box, add the U-Boot First State Boot Loader (FSBL) hex file (.hex).
  10. To add other data, such as a U-Boot Second Stage Boot Loader (SSBL) file or Phase 2 bitstreams:
    1. Click Add Raw Data and specify an Intel-format hexadecimal (.hex) file.
    2. Select the file you added and click Properties.
    3. In the Input File Properties dialog box, set the Bit swap field to On.

    Your Phase 1 and Phase 2 bitstreams are subject to the following restrictions:

  11. To specify the .sof file that occupies the flash memory partition, click Add Partition on the Configuration Device tab. Add Partition Dialog Box (Programming File Generator) describes all options.
    Figure 23. Add Flash Partition
  12. To select a supported flash memory device and predefined programming flow, click Add Device on the Configuration Device tab. Alternatively, click <<new device>> to define a new flash memory device and programming flow. Configuration Device Tab Settings describes all settings.
  13. Click the Select button for Flash Loader and select the device that controls loading of the flash memory device. Select Devices (Flash Loader) Dialog Box describes all settings.
  14. After you specify all options in Programming File Generator, the Generate button enables. Click Generate to create the files.
  15. Optional: Optional: Export your settings to a PFG setting file (.pfg) so that you can use these settings again with the quartus_pfg command line tool.

    For details, refer to quartus_pfg Command Line Tool.