P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683038
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples x
1.1. Overview 1.2. Functional Description for the Programmed Input/Output (PIO) Design Example 1.3. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.4. Functional Description for the Performance Design Example 1.5. Hardware and Software Requirements
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Compiling the Design Example 2.5. Installing the Linux Kernel Driver 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Testbench
2.3.1. Testbench x
2.3.1.1. Test Driver Module 2.3.1.2. PIO Design Example Testbench 2.3.1.3. SR-IOV Design Example Testbench 2.3.1.4. Performance Design Example Testbench
2.6. Running the Design Example x
2.6.1. Running the PIO Design Example 2.6.2. Running the SR-IOV Design Example 2.6.3. Running the Performance Design Example
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

2.3.1.2. PIO Design Example Testbench

The figure below shows the PIO design example simulation design hierarchy. The tests for the PIO design example are defined with the apps_type_hwtcl parameter set to 3. The tests run under this parameter value are defined in ebfm_cfg_rp_ep_rootport, find_mem_bar and downstream_loop.

Figure 20. PIO Design Example Simulation Design Hierarchy
The testbench starts with link training and then accesses the configuration space of the IP for enumeration. A task called downstream_loop (defined in the Root Port PCIe BFM altpcietb_bfm_rp_gen4_x16.sv) then performs the PCIe link test. This test consists of the following steps:
  1. Issue a memory write command to write a single dword of data into the on-chip memory behind the Endpoint.
  2. Issue a memory read command to read back data from the on-chip memory.
  3. Compare the read data with the write data. If they match, the test counts this as a Pass.
  4. Repeat Steps 1, 2 and 3 for 10 iterations.

The first memory write takes place around 219 us. It is followed by a memory read at the Avalon® -ST RX interface of the P-tile Hard IP for PCIe. The Completion TLP appears shortly after the memory read request at the Avalon® -ST TX interface.

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