1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
2.4. Compiling the Design Example
- Navigate to <project_dir>/intel_pcie_ptile_ast_0_example_design/ and open pcie_ed.qpf.
- If you select either of the two following development kits, the VID-related settings are included in the .qsf file of the generated design example, and you are not required to add them manually. Note that these settings are board-specific.
- Intel® Stratix® 10 DX P-Tile ES1 FPGA development kit
- Intel® Stratix® 10 DX P-Tile Production FPGA development kit
- Intel® Agilex™ F-Series P-Tile ES0 FPGA development kit
- On the Processing menu, select Start Compilation.
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