P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683038
Date 3/28/2022

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2.6.2. Running the SR-IOV Design Example

Here are the steps to test the SR-IOV design example on hardware:
  1. Run the Intel FPGA IP PCIe link test by running the sudo ./intel_fpga_pcie_link_test command and then select the option 1: Manually select a device.
  2. Enter the BDF of the physical function for which the virtual functions are allocated.
  3. Enter BAR “0” to proceed to the test menu.
  4. Enter option 7 to enable SR-IOV for the current device.
  5. Enter the number of virtual functions to be enabled for the current device.
  6. Enter option 8 to perform a link test for every enabled virtual function allocated for the physical function. The link test application will do 100 memory writes with a single dword of data each and then read the data back for checking. The application will print the number of virtual functions that failed the link test at the end of the testing.

  7. In a new terminal, run the lspci –d 1172: | grep -c “Altera” command to verify the enumeration of PFs and VFs. The expected result is the sum of the number of physical functions and number of virtual functions.