P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683038
Date 3/28/2022

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2.2. Generating the Design Example

Figure 13. Procedure
  1. In the Intel® Quartus® Prime Pro Edition software, create a new project (File > New Project Wizard).
  2. Specify the Directory, Name, and Top-Level Entity.
  3. For Project Type, accept the default value, Empty project. Click Next.
  4. For Add Files click Next.
  5. For Family, Device & Board Settings under Family, select Intel® Agilex™ or Intel® Stratix® 10 .
  6. If you selected Intel® Stratix® 10 in the last step, select Stratix 10 DX in the Device pull-down menu.
  7. Select the Target Device for your design.
  8. Click Finish.
  9. In the IP Catalog locate and add the Intel P-Tile Avalon® -ST Hard IP for PCI Express* .
  10. In the New IP Variant dialog box, specify a name for your IP. Click Create.
  11. On the Top-Level Settings and PCIe* Settings tabs, specify the parameters for your IP variation. Note: The Performance design example supports the Gen4 x16, 512-bit interface Hard IP mode.
  12. If you are using the SR-IOV design example, do the following steps to enable SR-IOV:
    1. On the PCIe* Device tab under the PCIe* PCI Express / PCI Capabilities tab, check the box Enable multiple physical functions.
    2. On the PCIe* Multifunction and SR-IOV System Settings tab, check the box Enable SR-IOV support and specify the number of PFs and VFs.
      For x8 configurations, check the boxes Enable multiple physical functions and Enable SR-IOV support for both PCIe0 and PCIe1 tabs.
    3. On the PCIe* MSI-X tab under the PCIe* PCI Express / PCI Capabilities tab, enable the MSI-X feature as required.
    4. On the PCIe* Base Address Registers tab, enable BAR0 for both PF and VF.
    5. Other parameter settings are not supported for this design example.
  13. On the Example Designs tab, make the following selections:
    1. For Example Design Files, turn on the Simulation and Synthesis options. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the example design generation time.
    2. For Generated HDL Format, only Verilog is available in the current release.
    3. For Target Development Kit, select either the Intel® Stratix® 10 DX P-Tile ES1 FPGA Development Kit, the Intel® Stratix® 10 DX P-Tile Production FPGA Development Kit or the Intel® Agilex™ F-Series P-Tile ES0 FPGA Development Kit.
    4. For Currently Selected Example Design, select PIO/SRIOV or Performance Design.
  14. Select Generate Example Design to create a design example that you can simulate and download to hardware. If you select one of the P-Tile development boards, the device on that board overwrites the device previously selected in the Intel® Quartus® Prime project if the devices are different. When the prompt asks you to specify the directory for your example design, you can accept the default directory, ./intel_pcie_ptile_ast_0_example_design, or choose another directory.
    Figure 14. Example Designs Tab
  15. Close the window when the design example generation is done. You may save your .ip file when prompted, but it is not required to be able to use the example design.
  16. Open the example design project by navigating to <project_dir>/intel_pcie_ptile_ast_0_example_design/ and opening the file pcie_ed.qpf.
  17. Compile the example design project to generate the .sof file for the complete example design. This file is what you download to a board to perform hardware verification. For details on how to compile the design, refer to Compiling the Design Example.
  18. Close your example design project.
    Note that you cannot change the PCIe pin allocations in the Intel® Quartus® Prime project. However, to ease PCB routing, you can take advantage of the lane reversal and polarity inversion features supported by this IP.