Cyclone® V GX, GT, and E Device Errata

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ID 683015
Date 8/01/2023
Public
Document Table of Contents
Document Table of Contents x
1. Cyclone V GX, GT, and E Device Errata
1. Cyclone V GX, GT, and E Device Errata x
1.1. TLP Corruption in x2 Mode 1.2. JTAG Programming of 28-nm Devices 1.3. Signal Detect Issue in PCIe Configuration 1.4. External Memory Interface (EMIF) Maximum Frequency Specification Update 1.5. Fractional PLL Phase Alignment Error 1.6. Configuration via Protocol (CvP) 1.7. Usermode High Icc 1.8. False Configuration Failure in Active Serial Multi-Device Configuration x1 Mode 1.9. Revision History for Cyclone® V GX, GT, and E Device Errata
1. Cyclone V GX, GT, and E Device Errata

1.8. Revision History for Cyclone V GX, GT, and E Device Errata

Date Version Changes
March 2018 2018.03.05 Made the following changes:
  • Updated the related information link in the "Signal Detect Issue in PCIe Configuration" section.
April 2017 2017.04.19 Made the following changes:
  • Corrected the URL to the fPLL evaluation tool in the "Fractional PLL Phase Alignment Error" section.
March 2017 2017.03.27 Made the following changes:
  • Changed the status to show correct list of affected devices.
March 2017 2017.03.15 Made the following changes:
  • Added the "Signal Detect Issue in PCIe Configuration" section.
September 2015 2015.09.18 Made the following changes:
  • Added the "JTAG Programming of 28-nm Devices" section.
April 2015 2015.04.03 Made the following changes:
  • Restructured and reformatted the document.
  • Removed the "SEU Internal Scrubbing" section.
  • Removed all SoC-related errata. This content is provided in the Cyclone V SX, ST and E SoC Device Errata document.
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