Cyclone® V GX, GT, and E Device Errata

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ID 683015
Date 8/01/2023
Public
Document Table of Contents
Document Table of Contents x
1. Cyclone V GX, GT, and E Device Errata
1. Cyclone V GX, GT, and E Device Errata x
1.1. TLP Corruption in x2 Mode 1.2. JTAG Programming of 28-nm Devices 1.3. Signal Detect Issue in PCIe Configuration 1.4. External Memory Interface (EMIF) Maximum Frequency Specification Update 1.5. Fractional PLL Phase Alignment Error 1.6. Configuration via Protocol (CvP) 1.7. Usermode High Icc 1.8. False Configuration Failure in Active Serial Multi-Device Configuration x1 Mode 1.9. Revision History for Cyclone® V GX, GT, and E Device Errata
1. Cyclone V GX, GT, and E Device Errata

1.4. External Memory Interface (EMIF) Maximum Frequency Specification Update

Description

To achieve timing closure, the EMIF maximum frequency specification has been updated in the table below.

Table 1.  Cyclone V EMIF Maximum Frequency Specification Update
Note: In this table, the stated performances apply to component topology only. The DIMM topology is not supported on the hard controller.
Note: For changes to other variants and slower speed grades, refer to the External Memory Interface Spec Estimator.
Device Speed Grade Memory Type Memory Topology Depth Expansion Interface Type Original Maximum Spec (MHz) Updated Maximum Spec (MHz)

Cyclone V

GX/E

 -C6 DDR2 Component 2 Chip Selects Hard Controller 400 333

Cyclone V

GX/GT/E

 -A7 DDR2 Component 1 Chip Select Hard Controller 400 333

Cyclone V

GX/GT/E

 -A7 DDR2 Component 2 Chip Selects Hard Controller 333 300

Status

Affects: Cyclone® V GX, GT, and E devices

Status: No planned fix

Level Two Title