Cyclone® V GX, GT, and E Device Errata

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ID 683015
Date 8/01/2023
Public
Document Table of Contents
Document Table of Contents x
1. Cyclone V GX, GT, and E Device Errata
1. Cyclone V GX, GT, and E Device Errata x
1.1. TLP Corruption in x2 Mode 1.2. JTAG Programming of 28-nm Devices 1.3. Signal Detect Issue in PCIe Configuration 1.4. External Memory Interface (EMIF) Maximum Frequency Specification Update 1.5. Fractional PLL Phase Alignment Error 1.6. Configuration via Protocol (CvP) 1.7. Usermode High Icc 1.8. False Configuration Failure in Active Serial Multi-Device Configuration x1 Mode 1.9. Revision History for Cyclone® V GX, GT, and E Device Errata
1. Cyclone V GX, GT, and E Device Errata

1.2. JTAG Programming of 28-nm Devices

JTAG configuration of 28-nm devices does not operate correctly when you initiate a PAUSE_DR instruction during configuration. In this scenario, JTAG configuration fails when pausing configuration in the middle of the bit stream by entering into the PAUSE-DR state and continuing to clock the TCK input. The failure is indicated by CONF_DONE staying low after all of the data has been clocked into the FPGA while nSTATUS remains high.

The PAUSE-DR feature works correctly with normal IEEE 1149.1 JTAG test operations.

Workaround

If you require pausing in the middle of the bit stream during JTAG configuration, halt the TCK and do not enter the PAUSE-DR state. Restart the TCK when you resume the configuration.

Status

Affects: Cyclone® V GX, GT, and E devices

There is no planned fix for this issue.

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