仅对英特尔可见 — GUID： eis1415255650806
Ixiasoft
1.6.1.2. 创建LPM_DIVIDE模块
按照以下步骤创建lpm_divide模块：
- 在Tools菜单中，单击MegaWizard Plug-In Manager。
- 在MegaWizard插件管理器对话框中，选择Create a new custom megafunction variation，并点击Next。MegaWizard Plug-In Manager 页面显示。
- 在MegaWizard插件管理器页面，选择或验证该表中所示的配置设置。点击Next，从而进入下一个页面。
参数编辑器页面 参数 值 2a Which megafunction would you like to customize 在Arithmetic文件夹中，选择LPM_DIVIDE Which device family will you be using? Stratix Which type of output file do you want to create? VHDL What name do you want for the output file? lp_div Return to this page for another create operation Turned off 3 Currently selected device family Stratix IV Match project/default Turned on How wide should the ‘numerator’ input bus be? 8 How wide should the ‘denominator’ input bus be? 8 Numerator Representation 选择Unsigned Denominator Representation 选择Unsigned 4 Do you want to pipeline the function? 选择Yes, I want an output latency of 1 clock cycle Create an Asynchronous Clear input Turned off Create a Clock Enable input Turned off Which do you wish to optimize? 选择Default Optimization Always return a positive remainder? 选择Yes 5 Generate netlist Turned off 6 Variation file Turned on Quartus II IP file Turned on Quartus II symbol file (.bsf) Turned off Instantiation template file Turned on Verilog HDL black box file (_bb.v) Turned on AHDL Include file (.inc) Turned off VHDL component declaration file (.cmp) Turned on PinPlanner ports file (.PPF) Turned on - 点击Finish。
构建了lpm_divide模块。