仅对英特尔可见 — GUID: mwh1409959614624
Ixiasoft
1.6.4.3.1. VHDL状态机编码示例
以下状态机有五个状态。异步复位将变量state设置为state_0。
in1与in2的和是state_1和state_2中的状态机的一个输出。(in1 - in2)的差也用于state_1和state_2中。临时变量tmp_out_0和tmp_out_1存储in1与in2的和及差。在状态机的各种状态下使用这些临时变量可确保互斥状态之间的适当资源共享。
VHDL状态机
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY vhdl_fsm IS PORT( clk: IN STD_LOGIC; reset: IN STD_LOGIC; in1: IN UNSIGNED(4 downto 0); in2: IN UNSIGNED(4 downto 0); out_1: OUT UNSIGNED(4 downto 0) ); END vhdl_fsm; ARCHITECTURE rtl OF vhdl_fsm IS TYPE Tstate IS (state_0, state_1, state_2, state_3, state_4); SIGNAL state: Tstate; SIGNAL next_state: Tstate; BEGIN PROCESS(clk, reset) BEGIN IF reset = '1' THEN state <=state_0; ELSIF rising_edge(clk) THEN state <= next_state; END IF; END PROCESS; PROCESS (state, in1, in2) VARIABLE tmp_out_0: UNSIGNED (4 downto 0); VARIABLE tmp_out_1: UNSIGNED (4 downto 0); BEGIN tmp_out_0 := in1 + in2; tmp_out_1 := in1 - in2; CASE state IS WHEN state_0 => out_1 <= in1; next_state <= state_1; WHEN state_1 => IF (in1 < in2) then next_state <= state_2; out_1 <= tmp_out_0; ELSE next_state <= state_3; out_1 <= tmp_out_1; END IF; WHEN state_2 => IF (in1 < "0100") then out_1 <= tmp_out_0; ELSE out_1 <= tmp_out_1; END IF; next_state <= state_3; WHEN state_3 => out_1 <= "11111"; next_state <= state_4; WHEN state_4 => out_1 <= in2; next_state <= state_0; WHEN OTHERS => out_1 <= "00000"; next_state <= state_0; END CASE; END PROCESS; END rtl;