仅对英特尔可见 — GUID: mwh1409959577109
Ixiasoft
1.3.1. 推断乘法器
要推断乘法器功能,综合工具会检测乘法器逻辑并在英特尔FPGA IP core中进行实现,或者将逻辑直接映射到device atom。
对于包含DSP模块的器件,英特尔Quartus Prime综合能够根据器件使用情况,在DSP模块(而不是逻辑)中实现功能。英特尔Quartus Prime fitter也能够在DSP模块中布局输入和输出寄存器(即执行寄存器封装),以提高性能和区域利用率。
以下Verilog HDL和VHDL代码示例显示综合工具可以将有符号和无符号乘法器推断为IP core或DSP block atom。每个示例均适合一个DSP模块单元。另外,当发生寄存器封装时,不需要用于寄存器的额外逻辑单元。
Verilog HDL无符号乘法器
module unsigned_mult (out, a, b); output [15:0] out; input [7:0] a; input [7:0] b; assign out = a * b; endmodule
注: Verilog HDL中的signed声明是Verilog 2001 Standard的一个特性。
包括输入和输出寄存器的Verilog HDL有符号乘法器(Pipelining = 2)
module signed_mult (out, clk, a, b); output [15:0] out; input clk; input signed [7:0] a; input signed [7:0] b; reg signed [7:0] a_reg; reg signed [7:0] b_reg; reg signed [15:0] out; wire signed [15:0] mult_out; assign mult_out = a_reg * b_reg; always @ (posedge clk) begin a_reg <= a; b_reg <= b; out <= mult_out; end endmodule
包括输入和输出寄存器的VHDL无符号乘法器(Pipelining = 2)
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY unsigned_mult IS PORT ( a: IN UNSIGNED (7 DOWNTO 0); b: IN UNSIGNED (7 DOWNTO 0); clk: IN STD_LOGIC; aclr: IN STD_LOGIC; result: OUT UNSIGNED (15 DOWNTO 0) ); END unsigned_mult; ARCHITECTURE rtl OF unsigned_mult IS SIGNAL a_reg, b_reg: UNSIGNED (7 DOWNTO 0); BEGIN PROCESS (clk, aclr) BEGIN IF (aclr ='1') THEN a_reg <= (OTHERS => '0'); b_reg <= (OTHERS => '0'); result <= (OTHERS => '0'); ELSIF (rising_edge(clk)) THEN a_reg <= a; b_reg <= b; result <= a_reg * b_reg; END IF; END PROCESS; END rtl;
VHDL有符号乘法器
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY signed_mult IS PORT ( a: IN SIGNED (7 DOWNTO 0); b: IN SIGNED (7 DOWNTO 0); result: OUT SIGNED (15 DOWNTO 0) ); END signed_mult; ARCHITECTURE rtl OF signed_mult IS BEGIN result <= a * b; END rtl;