仅对英特尔可见 — GUID: mwh1409959593258
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1.4.3.1. 简单移位寄存器
本节中的示例显示了一个简单的,单比特宽,69比特长的移位寄存器。
英特尔Quartus Prime综合通过使用Shift Register Intel® FPGA IP实现寄存器(W = 1和M = 69),然后将此寄存器映射到器件中的RAM,这可以在专用RAM模块或者MLAB存储器中进行布局。如果寄存器的长度少于69比特,那么英特尔Quartus Prime综合在逻辑中实现移位寄存器。
Verilog HDL单比特宽,69比特长的移位寄存器
module shift_1x69 (clk, shift, sr_in, sr_out); input clk, shift; input sr_in; output sr_out; reg [68:0] sr; always @ (posedge clk) begin if (shift == 1'b1) begin sr[68:1] <= sr[67:0]; sr[0] <= sr_in; end end assign sr_out = sr[68]; endmodule
VHDL单比特宽,69比特长的移位寄存器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY shift_1x69 IS PORT ( clk: IN STD_LOGIC; shift: IN STD_LOGIC; sr_in: IN STD_LOGIC; sr_out: OUT STD_LOGIC ); END shift_1x69; ARCHITECTURE arch OF shift_1x69 IS TYPE sr_length IS ARRAY (68 DOWNTO 0) OF STD_LOGIC; SIGNAL sr: sr_length; BEGIN PROCESS (clk) BEGIN IF (rising_edge(clk)) THEN IF (shift = '1') THEN sr(68 DOWNTO 1) <= sr(67 DOWNTO 0); sr(0) <= sr_in; END IF; END IF; END PROCESS; sr_out <= sr(68); END arch;