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1. Introduction to the Avalon® Interface Specifications
2. Avalon® Clock and Reset Interfaces
3. Avalon® Memory-Mapped Interfaces
4. Avalon® Interrupt Interfaces
5. Avalon® Streaming Interfaces
6. Avalon® Streaming Credit Interfaces
7. Avalon® Conduit Interfaces
8. Avalon® Tristate Conduit Interface
A. Deprecated Signals
B. Document Revision History for the Avalon® Interface Specifications
2.1. Avalon® Clock Sink Signal Roles
2.2. Clock Sink Properties
2.3. Associated Clock Interfaces
2.4. Avalon® Clock Source Signal Roles
2.5. Clock Source Properties
2.6. Reset Sink
2.7. Reset Sink Interface Properties
2.8. Associated Reset Interfaces
2.9. Reset Source
2.10. Reset Source Interface Properties
5.1. Terms and Concepts
5.2. Avalon® Streaming Interface Signal Roles
5.3. Signal Sequencing and Timing
5.4. Avalon® -ST Interface Properties
5.5. Typical Data Transfers
5.6. Signal Details
5.7. Data Layout
5.8. Data Transfer without Backpressure
5.9. Data Transfer with Backpressure
5.10. Packet Data Transfers
5.11. Signal Details
5.12. Protocol Details
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3.4. Timing
The Avalon® -MM interface is synchronous. Each Avalon® -MM interface is synchronized to an associated clock interface. Signals may be combinational if they are driven from the outputs of registers that are synchronous to the clock signal. This specification does not dictate how or when signals transition between clock edges. Timing diagrams are devoid of fine-grained timing information.