Visible to Intel only — GUID: uob1486763646552
Ixiasoft
Visible to Intel only — GUID: uob1486763646552
Ixiasoft
3.5.6.2.1. minimumResponseLatency Timing Diagram with readdatavalid or writeresponsevalid
For interfaces with readdatavalid or writeresponsevalid, the default a one-cycle minimumResponseLatency can lead to difficulty closing timing on Avalon® -MM hosts.
Compatibility
Interfaces with the same minimumResponseLatency are interoperable without any adaptation. If the host has a higher minimumResponseLatency than the agent, use pipeline registers to compensate for the differences. The pipeline registers should delay readdata from the agent. If the agent has a higher minimumResponseLatency than the host, the interfaces are interoperable without adaptation.