Timing Analyzer Resource Center



The Timing Analyzer is an ASIC-strength static timing analyzer that supports the industry-standard Synopsys® Design Constraints (SDC) format. This page provides links to resources where you can learn more about the Timing Analyzer.

For a brief overview of the Timing Analyzer, refer to the Timing Analyzer section on the Verification and Board Level product feature page.

Search for known Timing Analyzer issues and technical support solutions visit Knowledge Database. You can also visit the Intel® Community Forum to connect to and discuss technical issues with other Intel® FPGA users.

For additional resources visit Intel® FPGA Support Resources page.

Timing Analyzer Resources

Table 1 provides links to available documentation on the Timing Analyzer.

Table 2 provides links to available training and demonstrations on the Timing Analyzer.