1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs
You can generate initial I/O timing data for Intel FPGA devices using the
Quartus® Prime software GUI or Tcl commands. Initial I/O timing data is
useful for early pin planning and PCB design. You can generate initial timing data for the
following relevant timing parameters to adjust the design timing budget when considering I/O
standards and pin placement.
I/O Timing Parameters
Input setup time (tSU)
Input hold time (tH)
tH Timing Parameters
input pin to input register data delay
+ input register micro setup time
- input pin to input register clock delay
- input pin to input register data delay
+ input register micro hold time
+ input pin to input register clock delay
Clock to output delay (tCO)
+ clock pad to output register delay
+ output register clock-to-output delay
+ output register to output pin delay
Generating initial I/O timing information includes the following steps:
1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device
Follow these steps to define and synthesize the minimum flip-flop logic
to generate initial I/O timing data:
Create a new project in
Quartus® Prime Pro Edition software version 19.3.
Click Assignments > Device, specify your target device Family and a Target
device. For example, select the AGFA014R24
Click File > New and create a Block Diagram/Schematic
To add components to the schematic, click the Symbol Tool button.
Figure 2. Insert Pins and Wires in Block Editor
Under Name, type DFF, and then click OK. Click in the Block Editor to insert the DFF symbol.
through 5 to add an Input_data input
pin, Clock input pin, and Output_data output pin.
To connect the pins to the DFF, click the Orthogonal
Node Tool button, and then draw wire lines between the pin and
Figure 3. DFF with Pin Connections
To synthesize the DFF, click Processing > Start > Start Analysis & Synthesis. Synthesis generates the minimum design netlist required to
obtain I/O timing Data.
1.2. Step 2: Define I/O Standard and Pin Locations
The specific pin locations and I/O standard you assign to the device pins
impacts the timing parameter values. Follow these steps to assign the pin I/O standard
and location constraints:
Click Assignments > Pin Planner.
Assign pin location and I/O standard constraints according to
your design specifications. Enter the Node
Location, and I/O Standard values for the pins in the design
in the All Pins spreadsheet.
Alternatively, drag node names into the Pin Planner package view.
Figure 4. Pin Locations and I/O Standards Assignments in Pin
To compile the design, click Processing > Start Compilation. The Compiler generates I/O timing information during full
To restore the .qar project
archive, launch the
Quartus® Prime Pro Edition
software and click Project > Restore Archived Project. Alternatively, run the following command line equivalent without
launching the GUI:
quartus_sh --restore <archive file>
The io_timing_<device>_restored directory now contains the
qdb subfolder and various files.
To run the script with the
Quartus® Prime Timing Analyzer, run the following command:
quartus_sta –t <device>.tcl
Wait for completion. The
script execution may require 8 hours or more because each change on I/O standard
or pin location requires design recompilation.
To view the timing parameter values, open the generated text files in
timing_files, with names such as