AN 775: Generating Initial I/O Timing Data: for Intel FPGAs
Version Information
Updated for: |
---|
Intel® Quartus® Prime Design Suite 19.3 |
1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs
Timing Parameter | Description |
---|---|
Input setup time (tSU) Input hold time (tH) |
tSU and
tH Timing Parameters
tSU = input pin to input register data delay + input register micro setup time - input pin to input register clock delay tH = - input pin to input register data delay + input register micro hold time + input pin to input register clock delay |
Clock to output delay (tCO) |
tCO
Timing Parameters
tCO = + clock pad to output register delay + output register clock-to-output delay + output register to output pin delay |
Generating initial I/O timing information includes the following steps:
- Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device
- Step 2: Define I/O Standard and Pin Locations
- Step 3: Specify Device Operating Conditions
- Step 4: View I/O Timing in Datasheet Report
1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device
- Create a new project in Intel® Quartus® Prime Pro Edition software version 19.3.
- Click Assignments > Device, specify your target device Family and a Target device. For example, select the AGFA014R24 Intel® Agilex™ FPGA.
- Click File > New and create a Block Diagram/Schematic File.
-
To add components to the schematic, click the Symbol Tool button.
Figure 2. Insert Pins and Wires in Block Editor
- Under Name, type DFF, and then click OK. Click in the Block Editor to insert the DFF symbol.
- Repeat 4 through 5 to add an Input_data input pin, Clock input pin, and Output_data output pin.
-
To connect the pins to the DFF, click the Orthogonal
Node Tool button, and then draw wire lines between the pin and
DFF symbol.
Figure 3. DFF with Pin Connections
- To synthesize the DFF, click Processing > Start > Start Analysis & Synthesis. Synthesis generates the minimum design netlist required to obtain I/O timing Data.
1.2. Step 2: Define I/O Standard and Pin Locations
- Click Assignments > Pin Planner.
-
Assign pin location and I/O standard constraints according to
your design specifications. Enter the Node
Name, Direction,
Location, and I/O Standard values for the pins in the design
in the All Pins spreadsheet.
Alternatively, drag node names into the Pin Planner package view.
Figure 4. Pin Locations and I/O Standards Assignments in Pin Planner
- To compile the design, click Processing > Start Compilation. The Compiler generates I/O timing information during full compilation.
1.3. Step 3: Specify Device Operating Conditions
- Click Tools > Timing Analyzer.
-
In the Task pane,
double-click Update Timing Netlist. The
timing netlist updates with full compilation timing information that accounts
for the pin constraints you make.
Figure 5. Task Pane in the Timing Analyzer
-
Under Set Operating
Conditions, select one of the available timing models, such as
Slow vid3 100C Model or Fast vid3 100C Model.
Figure 6. Set Operating Conditions in the Timing Analyzer
1.4. Step 4: View I/O Timing in Datasheet Report
- In the Timing Analyzer, click Reports > Datasheet > Report Datasheet.
-
Click OK.
Figure 7. Datasheet Report in Timing AnalyzerThe Setup Times, Hold Times, and Clock to Output Times reports appear under the Datasheet Report folder in the Report pane.
- Click each report to view the Rise and Fall parameter values.
- For a conservative timing approach, specify the maximum absolute value.
Determining I/O Timing Parameters from the Datasheet Report
In the following example Setup Times report, the fall time is greater than the rise time, therefore tSU=tfall .
In the following example Hold Times report, the absolute value of the fall time is greater than the absolute value of the rise time, therefore tH=tfall .
In the following example Clock to Output Times report, the absolute value of the fall time is greater than the absolute value of the rise time, therefore tCO=tfall .
1.5. Scripted I/O Timing Data Generation
Follow these steps to generate I/O timing information reflecting multiple I/O standards for Intel® Agilex™ , Intel® Stratix® 10, and Intel® Arria® 10 devices:
-
Download the appropriate
Intel®
Quartus® Prime project archive file for your target device family:
- Intel® Agilex™ devices—https://www.intel.com/content/dam/www/programmable/us/en/others/literature/an/io_timing_agilex_latest.qar
- Intel® Stratix® 10 devices—https://www.intel.com/content/dam/www/programmable/us/en/others/literature/an/io_timing_stratix10.qar
- Intel® Arria® 10 devices—https://www.intel.com/content/dam/www/programmable/us/en/others/literature/an/io_timing_arria10.qar
-
To restore the .qar project
archive, launch the
Intel®
Quartus® Prime Pro Edition
software and click Project > Restore Archived Project. Alternatively, run the following command line equivalent without
launching the GUI:
quartus_sh --restore <archive file>
The io_timing_<device>_restored directory now contains the qdb subfolder and various files. -
To run the script with the
Intel®
Quartus® Prime Timing Analyzer, run the following command:
quartus_sta –t <device>.tcl
Wait for completion. The script execution may require 8 hours or more because each change on I/O standard or pin location requires design recompilation. - To view the timing parameter values, open the generated text files in timing_files, with names such as timing_tsuthtco_<device>_<speed>_<IO_standard>.txt.
1.6. AN 775: Generating Initial I/O Timing Data Document Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2019.12.08 | 19.3 |
|
2016.10.31 | 16.1 |
|