Timing Analyer Collections

The Timing Analyzer supports collection application program interfaces (APIs) that provide easy access to ports, pins, cells, or nodes in the design. You can use collection APIs with any valid constraints or tool command language (Tcl) commands specified in the Timing Analyzer.

Table 1 describes the collection commands supported by the Timing Analyzer.

For more information on collections, refer to the Timing Analyzer chapter or the SDC & Timing Analyzer API Reference Manual (PDF).

Table 1. Collection Commands

Command Description
all_clocksReturns a collection of all clocks in the design.
all_inputsReturns a collection of input ports in the design.
all_outputsReturns a collection of all registers in the design.
get_cellsReturns a collection of cells in the design. All cell names in the collection match the specified pattern. Wildcards can be used to select multiple cells at the same time.
get_clocksReturns a collection of clocks in the design. When used as an argument to another command, such as the -from or -to of set_multicycle_path, each node in the clock represents all nodes clocked by the clocks in the collection. The default uses the specific node (even if it is a clock) as the target of a command.
get_keepersReturns a collection of keeper nodes (non-combinational nodes) in the design.
get_netsReturns a collection of nets in the design. All net names in the collection match the specified pattern. You can use wildcards to select multiple nets at the same time.
get_nodesReturns a collection of nodes in the design.
get_pinsReturns a collection of pins in the design. All pin names in the collection match the specified pattern. You can use wildcards to select multiple pins at the same time.
get_portsReturns a collection of ports (design inputs and outputs) in the design.
get_registersReturns a collection of registers in the design.

The following example shows various uses of the create_clock and create_generated_clock commands with collection commands.

# Create a simple 10 ns with clock with a 60 % duty cycle
create_clock -period 10 -waveform {0 6} -name clk [get_ports clk]
# The following multicycle applies to all paths ending at registers
# clocked by clk
set_multicycle_path -to [get_clocks clk] 2