From the possible hold relationships, the Timing Analyzer selects the hold relationship that is the most restrictive. The hold relationship with the smallest difference between the latch and launch edges (that is, latch– launch and not the absolute value of latch – launch) is selected because this determines the minimum allowable delay for the register-toregister path. For Figure 2, the hold relationship selected is Hold Check A2. The Timing Analyzer determines clock hold slack as shown in Equation 4.

*Equation 4*

Clock Hold Slack = Data Arrival Time – Data Required Time

Data Required Time = Clock Arrival Time +μt_{H} + Hold Uncertainty

Clock Arrival Time = Latch Edge + Clock Network Delay to Destination Register

Data Arrival Time = Launch Edge + Clock Network Delay to Source Register +μt_{CO}+ Register to Register Delay

If the data path is from an input port to an internal register, the Timing Analyzer uses the equations shown in Equation 5 to calculate the hold slack time.

*Equation 5*

Clock Setup Slack Time = Data Arrival Time – Data Required Time

Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Input Minimum Delay of Pin + Pin to Register Delay

Data Required Time = Latch Edge + Clock Network Delay to Destination Register + μt_{H}

If the data path is an internal register to an output port, the Timing Analyzer uses the equations shown in Equation 6 to calculate the hold slack time.

*Equation 6*

Clock Setup Slack Time = Data Arrival Time – Data Required Time

Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + μt_{CO} + Register to Pin Delay

Data Required Time = Latch Edge + Clock Network Delay to Destination Register – Output Minimum Delay of Pin

### Recovery and Removal

Recovery time is the minimum length of time an asynchronous control signal, for example, and preset, must be stable before the next active clock edge. The recovery slack time calculation is similar to the clock setup slack time calculation, but it applies asynchronous control signals. If the asynchronous control is registered, the Timing Analyzer uses Equation 7 to calculate the recovery slack time.

*Equation 7*

Recovery Slack Time = Data Required Time – Data Arrival Time

Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + μt_{CO}+ Register to Register Delay

Data Required Time = Latch Edge + Clock Network Delay to Destination Register – μt_{SU}

If the asynchronous control is not registered, the Timing Analyzer uses the equations shown in Equation 8 to calculate the recovery slack time.

*Equation 8*

Recovery Slack Time = Data Required Time – Data Arrival Time

Data Arrival Time = Launch Edge + Maximum Input Delay + Port to Register Delay

Data Required Time = Latch Edge + Clock Network Delay to Destination Register Delay – μt_{SU}

*Note*: If the asynchronous reset signal is from a port (device I/O), you must make an Input Maximum Delay assignment to the asynchronous reset pin for the Timing Analyzer Timing Analyzer to perform recovery analysis on that path.

Removal time is the minimum length of time an asynchronous control signal must be stable after the active clock edge. The Timing Analyzer removal time slack calculation is similar to the clock hold slack calculation, but it applies asynchronous control signals. If the asynchronous control is registered, the Timing Analyzer uses the equations shown in Equation 9 to calculate the removal slack time.

*Equation 9*

Removal Slack Time = Data Arrival Time – Data Required Time

Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + μt_{CO}of Source Register + Register to Register Delay

Data Required Time = Latch Edge + Clock Network Delay to Destination Register + μt_{H}

If the asynchronous control is not registered, the Timing Analyzer uses the equations shown in Equation 10 to calculate the removal slack time.

*Equation 10*

Removal Slack Time = Data Arrival Time – Data Required Time

Data Arrival Time = Launch Edge + Input Minimum Delay of Pin + Minimum Pin to Register Delay

Data Required Time = Latch Edge + Clock Network Delay to Destination Register +μt_{H}

*Note*: If the asynchronous reset signal is from a device pin, you must specify the Input Minimum Delay constraint to the asynchronous reset pin for the Timing Analyzer to perform a removal analysis on this path.

### Multicycle Paths

Multicycle paths are data paths that require more than one clock cycle to latch data at the destination register. For example, a register may be required to capture data on every second or third rising clock edge.

Figure 3 shows an example of a multicycle path between a multiplier’s input registers and output register where the destination latches data on every other clock edge. Refer to Timing Analyzer set_multicycle_path Command for information about the **set_multicycle_path** command.