PCI Express Reference Designs & Application Notes

Recommended for:

  • Device: Many

  • Quartus®: Unknown



PCIE and Intel Technology

PCI Express* (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 16.0 GT/s and beyond. Intel offers a unique combination of hardened and soft IP to provide superior performance and flexibility for optimal integration.


Intel FPGA Intellectual Property (IP) for PCI Express continues to scale as the PCI-SIG organization delivers next-generation specifications. Intel has been a member of PCI-SIG since 1992, and with each new generation of silicon, Intel continues to participate in PCI-SIG Compliance Workshops to ensure interoperability and conformance with current industry standards.

Intel offers FPGA IP function-based PCI Express IP solutions that are compliant with the Platform Designer.

P-Tile PCIe Hard IP successfully passed August ‘19 PCI-SIG Compliance Testing Event. Results posted on the PCI-SIG integrators webpage.

PCIe* Features for P-Tile Hard IP:

  • Complete protocol stack including the transaction, data link, and physical layers implemented as a Hard IP
  • Natively supports up to Gen4x16 for endpoint and root port modes
  • Port bifurcation capabilities: four x4s root port, two x8s endpoint
  • Supports TLP bypass mode in both upstream and downstream modes
  • Supports up to 512B maximum payload
  • 10 bit tag support for x16 controller only with maximum 512 outstanding NPRs
  • Separate Refclk with independent spread spectrum Clocking (SRIS)
    • Separate Refclk with no spread spectrum clocking (SRNS)
    • Common Refclk architecture
  • PCI Express advanced error reporting (PF only)
  • Supports D0 and D3 PCIe power states only
  • Lane margining at receiver
  • Retimers presence detection

Multifunction and Virtualization Features:

  • SR-IOV support (8 PFs, 2K VFs per each Endpoint)
  • VirtIO support via configuration intercept interface
  • Scalable I/O and shared virtual memory (SVM) support (future)
  • Access control service (ACS)
  • Alternative routing-ID interpretation (ARI)
  • Function level reset (FLR)
  • TLP processing hint (TPH)
  • Address Translation Services (ATS)
  • Process address space ID (PasID)

User Interface Features:

  • Avalon® streaming (Avalon-ST) /Avalon memory-mapped (Avalon-MM) user-side interfaces
  • User packet interface with separate header, data and prefix
  • User packet interface can handle up to two TLPs in any given cycle (x16 mode only)
  • Up to 512 outstanding non-posted requests (x16 core only)
  • Up to 256 outstanding non-posted requests (x8 and x4 cores)
  • Supports autonomous Hard IP mode
    • This mode allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into user mode are complete.
  • FPGA core configuration via PCIe link (CVP Init and CVP Update)

IP Debug Features:

  • Debug toolkit including the following features:
    • Protocol and link status information
    • Basic and advanced debugging capabilities including PMA register access and Eye viewing capability.

Driver Support:

  • Linux*/Windows* device drivers

  • CvP – Configuration via Protocol
  • PRoP – Partial Reconfiguration over PCI Express
  • SR-IOV – Single Root I/O Virtualization
  • DMA – Direct Memory Access