Optimization Support Resources

Intel's Quartus® Prime and Quartus II software includes a wide range of features to help you optimize your design for area and timing. This page provides resources to help you with design optimization, physical synthesis, and Design Space Explorer (DSE).

The Quartus Prime and Quartus II software offers physical synthesis netlist optimization to optimize designs further than the standard compilation process. Physical synthesis helps improve the performance of your design, regardless of the synthesis tool used.

DSE automates the search for the settings that give the best results in any individual design. DSE explores the design space of your design, applies various optimization techniques, and analyzes the results to help you discover the best settings for your design.

For a brief overview and demo of the incremental compilation feature, refer to the Optimization product feature page.

To search for known optimization issues and technical support solutions, use Intel's Knowledge Database. You can also visit the Intel® Forum to connect and discuss technical issues with other Intel users.

For further technical support, use mySupport to create, view, and update service requests.

Design Optimization Resources

Design optimization can help you improve performance to reduce resource usage, close timing, and reduce compilation times. Table 1 lists the available optimization support documentation.

Table 1. Optimization Support Documentation

Title Description
Area and Timing Optimization This handbook chapter explains techniques to reduce resource usage, reduce compilation times, and improve timing performance when designing for Intel devices.
Analyzing and Optimizing the Design Floorplan This handbook chapter describes how you can use the chip planner to analyze and optimize the floorplan for your designs. This chapter also explains how to use Logic Lock Region to control the placement.
Engineering Change Management with the Chip Planner This handbook chapter describes using the chip planner to implement engineering change orders (ECOs) for supported devices.
Netlist Optimizations and Physical Synthesis This handbook chapter explains how the netlist optimizations and physical synthesis in Quartus Prime software can modify your design’s netlist and help improve the quality of your results.
Synthesis and Netlist Viewer Resource Center Following recommended coding guidelines can be a powerful way to obtain good quality results. Refer to the Design and Coding Guidelines section in the Synthesis and Netlist Viewer Resource Center for more information.
Incremental Compilation Resource Center

You can use incremental compilation to reduce compilation times and preserve results during optimization.

Table 2 provides links to training and demonstrations on the features and usage of optimization resources.

Table 2. Optimization Support Training Courses and Demonstrations

Title Description
Optimization Advisor

See a quick demonstration on the Quartus II software optimization advisor.

This is a 4-minute online demonstration.

The Quartus II Software Design Series: Foundation
(Instructor-Led Course)

The Quartus II Software Design Series: Foundation
(Online Training)

Learn how to use Quartus II software to develop an FPGA or CPLD. Create a new project, enter in new or existing design files, compile, and configure your device using the programmer to see the design working in-system. Learn how to apply timing constraints to your design and analyze your design using the TimeQuest timing analyzer, the static timing analyzer in the Quartus II software.

You will also learn techniques that help you plan your design and understand how Quartus II software interfaces with common EDA tools used for synthesis and simulation.

This is an 8-hour instructor-led course.

Using the Quartus II Software: Chip Planner
(Online Course)

Learn about the chip planner tasks, layers, and views, and how to perform design analysis with chip planner. See how to view critical paths and physical timing estimates. You will also see how to use chip planner to perform power analysis and to view routing congestion.

You will also learn how to perform ECOs and to work with floorplan assignments.

This is a 1.5-hour online course.

Timing Closure Using Quartus II Advisors and Design Space Explorer (Online Course)

Learn how to use the Quartus II Timing Optimization Advisor to find appropriate settings for your design for timing closure and the Quartus II DSE, an automated tool that helps you pick the best settings for your design to aid you in the timing closure process.

This is a 1-hour online course.

Best HDL Design Practices for Timing Closure (Online Course)

Learn how to address timing closure issues with HDL design techniques.

This is a 1-hour online course.