The Timing Analyzer is an ASIC-strength static timing analyzer that supports the industry-standard Synopsys® Design Constraints (SDC) format. This page provides links to resources where you can learn more about the Timing Analyzer.
For resources on the Timing Analyzer, see the following:
To search for known Timing Analyzer issues and technical support solutions, use Altera's Knowledge Database. You can also visit the Altera® Forum to connect to and discuss technical issues with other Altera users.
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Timing Analyzer Resources
Table 1 provides links to available documentation on the Timing Analyzer.
You will use the Timing Analyzer static timing analyzer tool in the Quartus II software to verify performance of an FPGA or HardCopy® ASIC. You will also create timing constraints (i.e., assignments) using the Timing Analyzer analyzer. You will use supported SDCs and generate timing reports from the Timing Analyzer analyzer's user interface and from script files.
This training shows you how to constrain and analyze single data rate source-synchronous interfaces with the Timing Analyzer timing analyzer in the Quartus II software. You will learn the benefits of source-synchronous interfaces as compared to common clock system interfaces. You will be able to write SDC constraints to constrain single data-rate, source-synchronous inputs and outputs. You will also learn to use the Timing Analyzer timing analyzer to report and analyze timing for source-synchronous outputs and inputs.
This training provides an introduction to double data rate interfaces and some of the challenges involved in constraining them. You’ll learn about clock constraints, data constraints, and timing exceptions for both input and output DDR interfaces. Finally, you’ll learn how to analyze DDR source synchronous interface timing with the Timing Analyzer timing analyzer.
You will learn how to use the Quartus II software to develop an FPGA or CPLD. You will create a new project, enter in new or existing design files, compile to your target FPGA or CPLD, and configure your device using the Quartus II programmer to see the design working in-system. You will also enter basic internal and I/O timing constraints and analyze a design for these timing constraints using the Timing Analyzer, the timing analyzer in the Quartus II software.
You will learn advanced features of the Quartus II software that will enable you to verify your FPGA design. You will learn how to constrain and analyze a design for timing, including understanding FPGA timing parameters, writing SDC files, generating various timing reports in the Timing Analyzer timing analyzer, and applying this knowledge to an FPGA design. You will also estimate FPGA power consumption using Quartus II software tools and EDA simulation tools.