About the Chip Planner

The Chip Planner provides a visual display of chip resources. It can show logic placement, LogicLock regions, relative resource usage, detailed routing information, fan-ins and fan-outs, paths between registers, and high-speed transceiver channels. You can view physical timing estimates, routing congestion, and clock regions.

The Chip Planner can perform assignment changes, such as creating and deleting resource assignments, as well as post-compilation changes, such as creating, moving, and deleting logic cells and I/O atoms. You can use the Chip Planner in conjunction with the Resource Property Editor, to change connections between resources and make post-compilation changes to the properties of logic cells, I/O elements, and PLLs.

To open the Chip Planner, you can click Chip Planner on the Tools menu. The Chip Planner is available for supported device families.

The Chip Planner displays resource usage on the current device. The displayed representation of chip resources varies somewhat depending on the device family. The level of detail shown in the Chip Planner depends on the current zoom level, as well as on the current settings selected in the Layers Settings dialog box.

The Chip Planner view is interactive; you can display design elements by generating reports in the Tasks pane; you can select resources in the Chip Planner using the Selection Tool from the toolbar. You can right-click a selected resource to display the Shortcut menu, which contains commands that you can apply to the resource. If you want to move a selected resource, you can drag and drop it to a new location.

In the Chip Planner, the term preset denotes a predefined set of display parameters, comprising a background color map and a selected set of layers. A layer represents a particular type of resource objects, such as logic elements, labels, partitions, or regions.

The Chip Planner includes six presets, which are available in the Preset list: Basic, Design Partition Planner, Detailed, Floorplan Editing, Power, and Routing Congestion. You can choose one of these presets, or you can use the Layers Settings dialog box to create custom presets to display only the resources of interest for a particular purpose; similarly, in the Layers Settings dialog box, you can choose a background color map to facilitate the display and editing of particular types of information.

The term task denotes a command used to display attributes of the device and your design. In the Tasks window, you can run tasks to display device resources, design partitions, routing utilization, clocks, pins, and transceiver resources, to locate entities mentioned in Compilation Messages, and to display any set of resources you select.

The Chip Planner has two editing modes that determine the types of operations that you can perform:

Assignment—Allows you to make changes that are applied by the Fitter during the next place-and-route operation. Typically, such changes include pin, LogicLock region, and location assignments. The Chip Planner can make assignment changes when operating in the Assignment editing mode.
ECO—Allows you to make post-compilation changes, also referred to as engineering change orders (ECOs). An ECO is a change made to a compiled design; such changes are not recognized by the Fitter, and are lost after the next compilation. Typically, such changes include minor placement, routing, or connectivity changes. The Chip Planner can make post-compilation changes when operating in the ECO editing mode.

When working with the Chip Planner, select a layer setting and an editing mode appropriate for the work that you want to perform. If you want to work with assignments, you might select a layer setting that shows regions and general density of resource usage, but minimal resource detail. Use this layer setting with the Assignment editing mode. If you want to make detailed changes to placement and routing, select a layer setting that shows detailed resource information and use the ECO editing mode.

The Bird's Eye View is a secondary window that displays a high-level view of resource usage over the entire device. The Bird's Eye View is linked to the main Chip Planner window so that you can rapidly navigate to points of interest in the main window by clicking the target location in the Bird's Eye View.

You can customize the detail displayed in the main Chip Planner window and the Bird's Eye View with the Layers Settings dialog box.

The Chip Planner displays resources you might want to change. The Location Assignments window allows you to make assignments to resources. You can make assignments to specific resources by dragging and dropping resources from the Chip Planner main window to the Location Assignments window.

The LogicLock Regions window allows you to assign resources to LogicLock regions. You can assign a resource to a LogicLock region by dragging and dropping a resource fromthe Chip Planner main window to a LogicLock region name in the LogicLock Regions window.

You can use the Resource Property Editor to optimize the design by making post-compilation changes to the properties of logic cells, I/O elements, and PLLs, and by changing connections between resources. The Change Manager maintains a record of all post-compilation changes, and allows you to undo changes if necessary.

Important: The Change Manager tracks post-compilation changes—that is, changes made in ECO mode. Changes made in Assignment mode, such as location assignments, are pre-Fitter changes that are not recorded in the Change Manager and cannot be undone automatically.