You can create LogicLock regions in the LogicLock Regions window, the Project Navigator, the Chip Planner, and the Design Partition Planner. You can also create LogicLock regions with the ::quartus::incremental_compilation API functions for Tcl.

You can assign nodes and entities to LogicLock regions by dragging and dropping them from the Node Finder or from the Hierarchy tab in the Project Navigator. You can edit LogicLock region assignments with the LogicLock Regions window. You can also create and edit assignments with the ::quartus::incremental_compilation Tcl package.  Nodes that are not user-assigned to another region and nodes that the Fitter moves from a user-assigned region are placed in the root region. In general, nodes not assigned to any region are placed in the root region. The root region encompasses the entire device and is locked. You can make assignments to the root region in the LogicLock Regions window, but you cannot delete it or modify its size or location.

When you assign an entity to a LogicLock region, all lower-level entities and nodes contained in that entity inherit the assignment. However, pins contained in that entity do not inherit the assignment. You can prevent a node or entity from inheriting a higher-level LogicLock region assignment by assigning the node or entity to the root region. You can prevent all nodes of a specific resource type from inheriting a LogicLock region assignment in the Excluded Element Types dialog box.

In the LogicLock Region Properties dialog box, you can add wildcard assignments to selected LogicLock regions. The availability of wildcard assignments makes it possible to create conflicting membership assignments between LogicLock regions. To ensure that such potential conflicts are handled in an orderly fashion, the Quartus II software applies assignments in a predetermined order of precedence. For more information, refer to Understanding Assignment Priority.

LogicLock back-annotation allows you preserve the location of nodes within a LogicLock region relative to the edges of the region. When you move a back-annotated region, its member nodes maintain their relative placement in the new location.

A LogicLock region can have a user-determined, fixed size, or a Fitter-determined, automatic size. The Quartus II software determines the size of automatically sized LogicLock regions during compilation, based on the resources required to implement the design entities specified for inclusion in the region. Fixed-sized LogicLock regions can have a locked or floating location. Auto-sized LogicLock regions must have a floating location. The Quartus II software determines the location for floating regions during compilation. You can preserve the size or location of regions for reuse in subsequent compilations.

The Fitter permits locked LogicLock regions to overlap with other LogicLock regions. However, the Fitter cannot place a floating LogicLock region in a location that causes it to overlap with other floating LogicLock regions except its ancestor and descendant regions. If a LogicLock region partially overlaps with an M512 memory block, or DSP block, the LogicLock region is considered to contain the whole block, and the Fitter might place nodes assigned to the LogicLock region anywhere on the overlapping block.

The Reserved option prevents the Fitter from placing nodes not assigned to the LogicLock region within the LogicLock region. To support team-based design, you can reserve areas of a device by creating a reserved LogicLock region without assigning nodes or entities to the LogicLock region.

You can construct a LogicLock region hierarchy by creating child regions inside of parent regions. You might want to create a LogicLock hierarchy to parallel your project's design hierarchy or to further guide placement. For example, you can try to optimize the performance of an entity by constraining the entity to a parent LogicLock region and constraining all nodes on the entity's critical path to a smaller child LogicLock region inside the parent region.

When you make one region the parent of another region, you place the child region inside the parent region. For this reason, the Quartus II software does not allow you to make a smaller region the parent of a larger region. The Quartus II software does not allow a child region to be located outside the parent region's boundary.

Once you specify the parent region for a LogicLock region, the Quartus II software interprets the child region's location as relative to its parent region's origin. When you lock the location of a child region, the child region's location is locked relative only to its parent's origin, not relative to the target device. When you move a parent region to a new location, the Quartus II software updates the locations of the region's descendant regions to maintain their positions relative to the parent region. When you resize a region, the Quartus II software checks that the new dimensions retain all the region's descendants and do not exceed the boundaries of its parent region. The Fitter requires that you assign floating locations to any child LogicLock regions that have an auto-size parent LogicLock region.

The Quartus II software performs LogicLock back-annotation recursively on the LogicLock region hierarchy — when you back-annotate a region's contents, the Quartus II software automatically back-annotates the contents of the region's descendant regions.

Altera recommends that you assign each design partition to a LogicLock region to improve quality of results when performing incremental compliation. As you change LogicLock region assignments and settings to refine your design, it is important to consider that the Netlist Type settings (as set in the Design Partitions window) of the partition determine whether those assignments are implemented in the next compilation or the previous assignments are preserved. For more information, refer to Understanding Assignment Priority.

For the design separation flow, the Quartus II software provides three LogicLock region types:

• Secured

• Security routing interface

• Unsecured

A secured LogicLock region restricts routing resources and creates a boundary of unused logic array blocks (LABs) around it. Each signal that enters or exits a secured LogicLock region must be assigned to an abutting security routing interface. By restricting routing resources and providing a boundary of unused resources, faults and unintended signals originating in one secured region are prevented from adversely affecting any other block on the device. Secured LogicLock regions are available for only Cyclone III LS devices.

A security routing interface is a LogicLock region that abuts a secured LogicLock region. Signals must enter a secure LogicLock region through a security routing interface. No logic can be assigned to a security routing interface. Security routing interfaces are available for only Cyclone III LS devices.

An unsecured LogicLock region does not create a boundary of unused LABs, and does not have routing restrictions. Unsecured LogicLock regions are available for supported device(Arria series, Cyclone series, MAX II, and Stratix series) families.