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Layers Settings Dialog Box |
You open this dialog box by clicking Layers Settings on the View menu. |
Allows you to create, delete, and modify layer settings, which determine the objects displayed in the Chip Planner.
Specifies the name of the current layer settings and allows you to create, delete, or reset a preset layer.
Preset— Specifies the name of the current preset. Modified presets are marked with an asterisk.
Save— Allows you to save the current preset. If you specify a new name for a modified preset, it is saved as a new preset.
Delete— Deletes the current preset.
Reset— Discards any unsaved changes to the current default preset.
Reset All— Deletes any customized preset layer settings and restores default layer settings to their factory-original values.
Allows you to specify the graphic elements displayed for a given layer preset. When you turn on or off the display of graphic elements, the settings apply to both the Chip Planner view and the Bird's Eye View. When you turn off graphic elements you can increase window refresh speed and reduce visual clutter when viewing complex designs.
You can choose whether to display the following graphic elements:
Background— The background color indicating the relative level of resource usage for different areas of the device.
None— No background color map.
Block Utilization— Indicates relative block usage.
Design Partition Planner— Optimized for use in conjunction with the Design Partition Planner, to display the physical placement of design entities.
LogicLock Regions— Displays LogicLock regions.
User-assigned LogicLock Regions— User-assigned LogicLock regions.
Fitter-placed LogicLock Regions— Fitter-placed LogicLock regions.
Clock Regions— The regional clocks to be displayed in the Chip Planner. Regional clock display is available for supported device(Arria series, Cyclone III, Cyclone IV, Cyclone V, Stratix III, Stratix IV, and Stratix V) families.
Global Clock Region— Displays only global clock regions.
Local Clock Region— Displays only local clock regions.
LVDS Clock Region— Displays only LVDS clock regions.
Regional Clock Region— Displays only regional (quadrant) clock regions.
Periphery Clock Region— Displays only periphery (P) clock regions.
Overlay Objects— Additional objects to be displayed.
Connection Lines—Connections resulting from any of the Chip Planner's Generate commands.
Labels—Labels on displayed connections resulting from any of the Chip Planner's Generate commands.
Differential Pin Pairs—Differential pin pairs. The function of this control is similar to the Show Differential Pin Pair Connections command.
Report Overlay—Graphic elements resulting from any of the Chip Planner's generated reports.
Routing Details— Routing information.
Local Routing— Logic routing within blocks.
Global Routing— Logic routing between blocks.
Logic Details— Logic information.
Logic Details— Detailed display of logic features.
Ports— Ports.
Node Coloring— Coloring scheme for node display.
None— No node coloring.
Partition Based— Nodes are colored according to partition membership.
Utilization Level Based— Nodes are colored according to their level of utilization.
Other—Other objects to be displayed.
Unused Resources— Unused resources.
Pin and Location Assignments— Pin assignments and location assignments.
Copyright© 2005-2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.
