rst_mgr Address Map

Module Instance Base Address End Address
i_rst_mgr_rstmgr 0xFFD05000 0xFFD05FFF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
stat 0x0 32 RW 0x0 
Status Register
ramstat 0x4 32 RW 0x0 
RAM Status Register
miscstat 0x8 32 RW 0x0 
Status Register
ctrl 0xC 32 RW 0x100000 
Control Register
hdsken 0x10 32 RW 0x100000 
Control Register
hdskreq 0x14 32 RW 0x100000 
Control Register
hdskack 0x18 32 RW 0x100000 
Control Register
counts 0x1C 32 RW 0x80000800 
Reset Cycles Count Register
mpumodrst 0x20 32 RW 0x2 
MPU Module Reset Register
per0modrst 0x24 32 RW 0xFF7FFFFF 
Peripheral 0 Module Reset Register
per1modrst 0x28 32 RW 0x7031F3F 
Peripheral Module Reset Register
brgmodrst 0x2C 32 RW 0x7F 
Bridge Module Reset Register
sysmodrst 0x30 32 RW 0x0 
SYSTEM Module Reset Register
coldmodrst 0x34 32 RW 0x0 
COLD Module Reset Register
nrstmodrst 0x38 32 RW 0x0 
NRST Module Reset Register
dbgmodrst 0x3C 32 RW 0x0 
Debug Module Reset Register
mpuwarmmask 0x40 32 RW 0x1F 
MPU Warm Mask Register
per0warmmask 0x44 32 RW 0xFF7FFFFF 
Peripheral 0 Warm Mask Register
per1warmmask 0x48 32 RW 0x7031F3F 
Peripheral 1 Warm Mask Register
brgwarmmask 0x4C 32 RW 0x7F 
Bridge Warm Mask Register
syswarmmask 0x50 32 RW 0x1FF 
SYSTEM Warm Mask Register
nrstwarmmask 0x54 32 RW 0x1 
NRST Warm Mask Register
l3warmmask 0x58 32 RW 0x1 
Mask L3 Register
tststa 0x5C 32 RO 0x0 
Test Status
tstscratch 0x60 32 RW 0x0 
Test Scratch
hdsktimeout 0x64 32 RW 0x2800 
Hand Shake Time Out
hmcintr 0x68 32 RW 0x0 
HMC Interrupt
hmcintren 0x6C 32 RW 0x0 
HMC Interrupt enable
hmcintrens 0x70 32 RW 0x0 
HMC Interrupt enable set
hmcintrenr 0x74 32 RW 0x0 
HMC Interrupt Enable Clear
hmcgpout 0x78 32 RW 0x0 
HMC GPIO Output
hmcgpin 0x7C 32 RO 0x0 
HMC GPIO Input