per0warmmask

         The PER0WARMMASK register is used by software to mask the assertion of Peripheral and Fast Peripheral reset signals for hardware sequenced warm resets. There is a writeable bit for each module reset signal that is asserted by default on a hardware sequenced warm reset. If the bit is 1, the module reset signal is asserted by a hardware sequenced warm reset. If the bit is 0, the module reset signal is not changed by a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers match the corresponding *MODRST registers. Any module reset signals that are never asserted by a warm reset have reserved bit offsets and are tied to 0 (read as 0, writes are ignored).

All fields are only reset by a cold reset.
      
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD05000 0xFFD05044

Offset: 0x44

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

dmaif7

RW 0x1

dmaif6

RW 0x1

dmaif5

RW 0x1

dmaif4

RW 0x1

dmaif3

RW 0x1

dmaif2

RW 0x1

dmaif1

RW 0x1

dmaif0

RW 0x1

Reserved

emacptp

RW 0x1

dmaocp

RW 0x1

spis1

RW 0x1

spis0

RW 0x1

spim1

RW 0x1

spim0

RW 0x1

dma

RW 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

sdmmcocp

RW 0x1

qspiocp

RW 0x1

nandocp

RW 0x1

usb1ocp

RW 0x1

usb0ocp

RW 0x1

emac2ocp

RW 0x1

emac1ocp

RW 0x1

emac0ocp

RW 0x1

sdmmc

RW 0x1

qspi

RW 0x1

nand

RW 0x1

usb1

RW 0x1

usb0

RW 0x1

emac2

RW 0x1

emac1

RW 0x1

emac0

RW 0x1

per0warmmask Fields

Bit Name Description Access Reset
31 dmaif7
Masks hardware sequenced warm reset for DMA channel 7 interface adapter between FPGA Fabric and HPS DMA Controller
RW 0x1
30 dmaif6
Masks hardware sequenced warm reset for DMA channel 6 interface adapter between FPGA Fabric and HPS DMA Controller
RW 0x1
29 dmaif5
Masks hardware sequenced warm reset for DMA channel 5 interface adapter between FPGA Fabric and HPS DMA Controller
RW 0x1
28 dmaif4
Masks hardware sequenced warm reset for DMA channel 4 interface adapter between FPGA Fabric and HPS DMA Controller
RW 0x1
27 dmaif3
Masks hardware sequenced warm reset for DMA channel 3 interface adapter between FPGA Fabric and HPS DMA Controller
RW 0x1
26 dmaif2
Masks hardware sequenced warm reset for DMA channel 2 interface adapter between FPGA Fabric and HPS DMA Controller
RW 0x1
25 dmaif1
Masks hardware sequenced warm reset for DMA channel 1 interface adapter between FPGA Fabric and HPS DMA Controller
RW 0x1
24 dmaif0
Masks hardware sequenced warm reset for DMA channel 0 interface adapter between FPGA Fabric and HPS DMA Controller
RW 0x1
22 emacptp
Masks hardware sequenced warm reset for EMAC PTP
RW 0x1
21 dmaocp
Masks hardware sequenced warm reset for DMA Controller ECC OCP DIagnostics module.
RW 0x1
20 spis1
Masks hardware sequenced warm reset for SPIS1 controller
RW 0x1
19 spis0
Masks hardware sequenced warm reset for SPIS0 controller
RW 0x1
18 spim1
Masks hardware sequenced warm reset for SPIM1 controller
RW 0x1
17 spim0
Masks hardware sequenced warm reset for SPIM0 controller
RW 0x1
16 dma
Masks hardware sequenced warm reset for DMA controller
RW 0x1
15 sdmmcocp
Masks hardware sequenced warm reset for SDMMC ECC OCP DIagnostics module.
RW 0x1
14 qspiocp
Masks hardware sequenced warm reset for QSPI ECC OCP DIagnostics module.
RW 0x1
13 nandocp
Masks hardware sequenced warm reset for NAND ECC OCP DIagnostics modules.
RW 0x1
12 usb1ocp
Masks hardware sequenced warm reset for USB1 ECC OCP DIagnostics module.
RW 0x1
11 usb0ocp
Masks hardware sequenced warm reset for USB0 ECC OCP DIagnostics module.
RW 0x1
10 emac2ocp
Masks hardware sequenced warm reset for EMAC2 ECC OCP DIagnostics modules.
RW 0x1
9 emac1ocp
Masks hardware sequenced warm reset for EMAC1 ECC OCP DIagnostics modules.
RW 0x1
8 emac0ocp
Masks hardware sequenced warm reset for EMAC0 ECC OCP DIagnostics modules.
RW 0x1
7 sdmmc
Masks hardware sequenced warm reset for SD/MMC controller
RW 0x1
6 qspi
Masks hardware sequenced warm reset for QSPI flash controller
RW 0x1
5 nand
Masks hardware sequenced warm reset for NAND flash controller
RW 0x1
4 usb1
Masks hardware sequenced warm reset for USB1USB1
RW 0x1
3 usb0
Masks hardware sequenced warm reset for USB0
RW 0x1
2 emac2
Masks hardware sequenced warm reset for EMAC2
RW 0x1
1 emac1
Masks hardware sequenced warm reset for EMAC1
RW 0x1
0 emac0
Masks hardware sequenced warm reset for EMAC0
RW 0x1