hdskreq

         The CTRL register is used by software to control reset behavior.It includes fields for software to initiate the cold and warm reset, enable hardware handshake with other modules before warm reset, and perform software handshake. The software handshake sequence must match the hardware sequence. Software mustde-assert the handshake request after asserting warm reset and before de-assert the warm reset.

Fields are only reset by a cold reset.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD05000 0xFFD05014

Offset: 0x14

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

etrstallreq

RW 0x0

fpgahsreq

RW 0x0

fpgamgrhsreq

RW 0x0

sdrselfrefreq

RW 0x0

hdskreq Fields

Bit Name Description Access Reset
3 etrstallreq 
Software writes this field 1 to request to the ETR that it stalls its AXI master to the L3 Interconnect.

Software waits for the ETRSTALLACK to be 1 and then writes this field to 0.  Note that it is possible for the ETR to never assert ETRSTALLACK so software should timeout if ETRSTALLACK is never asserted.
 RW 0x0
2 fpgahsreq 
Software writes this field 1 to initiate handshake  request to FPGA .

Software waits for the FPGAHSACK to be active and then writes this field to 0.  Note that it is possible for the FPGA to never assert FPGAHSACK so software should timeout in this case.
 RW 0x0
1 fpgamgrhsreq 
Software writes this field 1 to request to the FPGA Manager to idle its output clock.

Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0.  Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so software should timeout in this case.
 RW 0x0
0 sdrselfrefreq 
Software writes this field 1 to request to the SDRAM Controller Subsystem that it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM contents across a software warm reset.

Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0.  Note that it is possible for the SDRAM Controller Subsystem to never assert SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted.
 RW 0x0