stat

         The STAT register contains bits that indicate the reset source. For reset sources, a field is 1 if its associated reset requester caused the reset. 

Software clears bits by writing them with a value of 1. Writes to bits with a value of 0 are ignored.

After a cold reset is complete, all bits are reset to their reset value except for the bit(s) that indicate the source of the cold reset. If multiple cold reset requests overlap with each other, the source de-asserts the request last will be logged. The other reset request source(s)  de-assert the request in the same cycle will also be logged, the rest of the fields are reset to default value of 0.

 After a warm reset is complete, the bit(s) that indicate the source of  the warm reset are set to 1. A warm reset doesn't clear any of the bits  in the STAT register; these bits must be cleared by software writing  the STAT register.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD05000 0xFFD05000

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cdbgreqrst

RW 0x0

fpgadbgrst

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

l4wd1rst

RW 0x0

l4wd0rst

RW 0x0

mpuwd1rst

RW 0x0

mpuwd0rst

RW 0x0

swwarmrst

RW 0x0

fpgawarmrst

RW 0x0

nrstpinrst

RW 0x0

Reserved

swcoldrst

RW 0x0

configiocoldrst

RW 0x0

fpgacoldrst

RW 0x0

nporpinrst

RW 0x0

porfpgavoltrst

RW 0x0

porhpsvoltrst

RW 0x0

stat Fields

Bit Name Description Access Reset
17 cdbgreqrst 
DAP triggered debug reset
 RW 0x0
16 fpgadbgrst 
FPGA triggered debug reset
 RW 0x0
14 l4wd1rst 
L4 Watchdog 1 triggered a hardware sequenced warm reset
 RW 0x0
13 l4wd0rst 
L4 Watchdog 0 triggered a hardware sequenced warm reset
 RW 0x0
12 mpuwd1rst 
MPU Watchdog 1 triggered a hardware sequenced warm reset
 RW 0x0
11 mpuwd0rst 
MPU Watchdog 0 triggered a hardware sequenced warm reset
 RW 0x0
10 swwarmrst 
Software wrote CTRL.SWARMRSTREQ to 1 and triggered a hardware sequenced warm reset.
 RW 0x0
9 fpgawarmrst 
FPGA core triggered a hardware sequenced warm reset
 RW 0x0
8 nrstpinrst 
nRST pin triggered a hardware sequenced warm reset
 RW 0x0
5 swcoldrst 
Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset.
 RW 0x0
4 configiocoldrst 
FPGA entered CONFIG_IO mode and a triggered a cold reset
 RW 0x0
3 fpgacoldrst 
FPGA core triggered a cold reset (f2s_cold_rst_req = 1)
 RW 0x0
2 nporpinrst 
nPOR pin triggered a cold reset (por_pin_req = 1)
 RW 0x0
1 porfpgavoltrst 
Built-in FPGA  POR voltage detector triggered a cold reset.  Security Manager brought Reset Manager out of POR Reset.
 RW 0x0
0 porhpsvoltrst 
Built-in HPS POR voltage detector triggered a cold reset.  Security Manager brought Reset Manager out of POR Reset.
 RW 0x0