hdsken

         The CTRL register is used by software to control reset behavior.It includes fields for enable hardware handshake with other modules before warm reset.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD05000 0xFFD05010

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

etrstallen

RW 0x0

fpgahsen

RW 0x0

fpgamgrhsen

RW 0x0

sdrselfrefen

RW 0x0

hdsken Fields

Bit Name Description Access Reset
3 etrstallen 
Software writes this field 1 to request to the ETR that it stalls its AXI master to the L3 Interconnect.

Software waits for the ETRSTALLACK to be 1 and then writes this field to 0.  Note that it is possible for the ETR to never assert ETRSTALLACK so software should timeout if ETRSTALLACK is never asserted.
 RW 0x0
2 fpgahsen 
This field controls whether to perform handshake with FPGA before asserting warm reset.
If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm reset signals. However if FPGA is already in warm reset state, the handshake is not performed.
If set to 0, the handshake is not performed
 RW 0x0
1 fpgamgrhsen 
Enables a handshake between the Reset Manager and FPGA Manager before a warm reset. The handshake is used to warn the FPGA Manager that a warm reset it coming so it can prepare for it. When the FPGA Manager receives a warm reset handshake, the FPGA Manager drives its output clock to a quiescent state to avoid glitches.
If set to 1, the  Manager makes a request to the FPGA Managerbefore asserting warm reset signals. However if the FPGA Manager is already in warm reset, the handshake is skipped.
If set to 0, the handshake is skipped.
 RW 0x0
0 sdrselfrefen 
This field controls whether the contents of SDRAM devices survive a hardware sequenced warm reset. If set to 1, the Reset Manager makes a request to the SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode before asserting warm reset signals. However, if SDRAM is already in warm reset, Handshake with SDRAM is not performed.
 RW 0x0